General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions.

[1]  V.G. Oklobdzija,et al.  Dynamic flip-flop with improved power , 2000, Proceedings 2000 International Conference on Computer Design.

[2]  V.G. Oklobdzija,et al.  A clock skew absorbing flip-flop , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  Vojin G. Oklobdzija,et al.  Dual-edge triggered storage elements and clocking strategy for low-power systems , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Bart R. Zeydel,et al.  Energy optimization of pipelined digital systems using circuit sizing and supply scaling , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[6]  Vojin G. Oklobdzija,et al.  High-performance energy-efficient microprocessor design , 2006 .

[7]  David G. Chinnery,et al.  Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design , 2002 .

[8]  J. Tschanz,et al.  Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[9]  R.W. Brodersen,et al.  Methods for true energy-performance optimization , 2004, IEEE Journal of Solid-State Circuits.

[10]  F. Weber,et al.  Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[11]  Samuel D. Naffziger,et al.  The implementation of the Itanium 2 microprocessor , 2002, IEEE J. Solid State Circuits.

[12]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[13]  Alain J. Martin.  Towards an energy complexity of computation , 2001, Inf. Process. Lett..

[14]  Tomás Lang,et al.  Individual flip-flops with gated clocks for low power datapaths , 1997 .

[15]  Vladimir Stojanovic,et al.  Digital System Clocking: High-Performance and Low-Power Aspects , 2003 .

[16]  V. Zyuban,et al.  Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels , 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

[17]  Ashutosh Das,et al.  A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors , 1999 .

[18]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[19]  Young-Hyun Jun,et al.  Conditional-capture flip-flop for statistical power reduction , 2001, IEEE J. Solid State Circuits.

[20]  V.G. Oklobdzija,et al.  The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements , 2007, IEEE Journal of Solid-State Circuits.

[21]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[22]  Robert W. Brodersen,et al.  Analysis and design of low-energy flip-flops , 2001, ISLPED '01.

[23]  Sung-Mo Kang,et al.  Noise constrained transistor sizing and power optimization for dual Vst domino logic , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[24]  Vojin G. Oklobdzija,et al.  High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems) , 2006 .

[25]  Vojin G. Oklobdzija,et al.  Conditional techniques for low power consumption flip-flops , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[26]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[27]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[28]  Massimo Alioto,et al.  Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Paul I. Pénzes,et al.  Energy-delay efficiency of VLSI computations , 2002, GLSVLSI '02.

[30]  E. You,et al.  A third-generation SPARC V9 64-b microprocessor , 2000, IEEE Journal of Solid-State Circuits.

[31]  Christopher Saint,et al.  IC Mask Design , 2002 .

[32]  Vojin G. Oklobdzija.  Clocking and clocked storage elements in a multi-gigahertz environment , 2003, IBM J. Res. Dev..

[33]  Tarek Darwish,et al.  High-performance and low-power conditional discharge flip-flop , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Nogawa,et al.  A Data-transition Look-ahead DFF Circuit For Statistical Reduction In Power Consumption , 1997 .

[35]  B. Nikolic.  Design in the Power-Limited Scaling Regime , 2008, IEEE Transactions on Electron Devices.

[36]  James Tschanz,et al.  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.

[37]  Manoj Sachdev,et al.  Low power, testable dual edge triggered flip-flops , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[38]  Krste Asanovic,et al.  Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy , 2007, IEEE Trans. Very Large Scale Integr. Syst..

[39]  Jan M. Rabaey,et al.  Digital integrated circuits: a design perspective / Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic , 2003 .

[40]  Krste Asanovic,et al.  Load-sensitive flip-flop characterizations , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.