Dynamic row activation mechanism for multi-core systems
暂无分享,去创建一个
[1] Chao Zhang,et al. Enabling efficient fine-grained DRAM activations with interleaved I/O , 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).
[2] Tareq A. Alawneh. A Dynamic Row-Buffer Management Policy for Multimedia Applications , 2019, 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).
[3] A. Azzouz. 2011 , 2020, City.
[4] Ahmed Elhossini,et al. A prefetch-aware memory system for data access patterns in multimedia applications , 2018, CF.
[5] Ahmed Elhossini,et al. A data access prediction unit for multimedia applications , 2016, 2016 28th International Conference on Microelectronics (ICM).
[6] A. James. 2010 , 2011, Philo of Alexandria: an Annotated Bibliography 2007-2016.
[7] Onur Mutlu,et al. A case for exploiting subarray-level parallelism (SALP) in DRAM , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[8] Aamer Jaleel,et al. HAPPY: Hybrid Address-based Page Policy in DRAMs , 2015, MEMSYS.
[9] Hyeonggyu Kim,et al. Partial Row Activation for Low-Power DRAM System , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[10] William J. Dally,et al. Architecting an Energy-Efficient DRAM System for GPUs , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[11] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[12] Lizy Kurian John,et al. Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[13] Bruce Jacob,et al. Fine-Grained Activation for Power Reduction in DRAM , 2010, IEEE Micro.
[14] O Seongil,et al. Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems , 2014, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis.
[15] Shyamkumar Thoziyoor,et al. CACTI 5 . 1 , 2008 .
[16] Norman P. Jouppi,et al. Rethinking DRAM design and organization for energy-constrained multi-cores , 2010, ISCA.
[17] Mark Horowitz,et al. Improving energy efficiency of DRAM by exploiting half page row access , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[18] R. Govindarajan,et al. Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities , 2012, ICS '12.
[19] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[20] Tom Feist,et al. Vivado Design Suite , 2012 .
[21] Yunsaing Kim,et al. A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture , 2012, 2012 IEEE International Solid-State Circuits Conference.
[22] Tao Zhang,et al. Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).