SIMD-Based Implementations of Sieving in Integer-Factoring Algorithms

The best known integer-factoring algorithms consist of two stages: the sieving stage and the linear-algebra stage. Efficient parallel implementations of both these stages have been reported in the literature. All these implementations are based on multi-core or distributed parallelization. In this paper, we experimentally demonstrate that SIMD instructions available in many modern processors can lead to additional speedup in the computation of each core. We handle the sieving stage of the two fastest known factoring algorithms (NFSM and MPQSM), and are able to achieve 15–40% speedup over non-SIMD implementations. Although the sieving stage offers many tantalizing possibilities of data parallelism, exploiting these possibilities to get practical advantages is a challenging task. Indeed, to the best of our knowledge, no similar SIMD-based implementation of sieving seems to have been reported in the literature.

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