A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram

Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, very low standby power and high storage density. Multi-level Cell (MLC) PRAM, which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As a first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error control coding (ECC) scheme can be used for half of the bits. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the remaining bits. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the proposed multi-tiered approach enables us to use ECC with 2-error correction capability (t = 2) instead of one with t = 8 to achieve a block failure rate (BFR) of 10−8. We propose to use a non-iterative algorithm to implement the BCH t = 2 decoder because of its small latency. We evaluate the latency and energy overhead of the proposed scheme using CACTI and the IPC performance using GEM5. We show that for SPEC CINT 2006 and DaCapo benchmarks, the proposed system can achieve BFR = 10−8 with 2.2 % IPC reduction and 7 % additional energy compared to a memory without any error correction capability.