HAP: A Heterogeneity-Conscious Runtime System for Adaptive Pipeline Parallelism
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[1] Vijay Janapa Reddi,et al. High-performance and energy-efficient mobile web browsing on big/little systems , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).
[2] Vanchinathan Venkataramani,et al. Hierarchical power management for asymmetric multi-core in dark silicon era , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[3] Michael I. Gordon,et al. Exploiting coarse-grained task, data, and pipeline parallelism in stream programs , 2006, ASPLOS XII.
[4] Steven Skiena,et al. The Algorithm Design Manual , 2020, Texts in Computer Science.
[5] Alfons Kemper,et al. Heterogeneity-conscious parallel query execution: getting a better mileage while driving faster! , 2014, DaMoN '14.
[6] Brian Jeff. Big.LITTLE system architecture from ARM: saving power through heterogeneous multiprocessing and task context migration , 2012, DAC.
[7] Onur Mutlu,et al. Bottleneck identification and scheduling in multithreaded applications , 2012, ASPLOS XVII.
[8] Muhammad Aater Suleman,et al. An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs , 2010 .
[9] Henry Hoffmann,et al. Application heartbeats: a generic interface for specifying program performance and goals in autonomous computing environments , 2010, ICAC '10.
[10] Yale N. Patt,et al. Feedback-directed pipeline parallelism , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).
[11] Woongki Baek,et al. HARS: A heterogeneity-aware runtime system for self-adaptive multithreaded applications , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[12] Harold Gumbel. Waiting Lines with Heterogeneous Servers , 1960 .
[13] Norman P. Jouppi,et al. Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[14] Rafael Asenjo,et al. Analytical Modeling of Pipeline Parallelism , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.
[15] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[16] Norman P. Jouppi,et al. Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures , 2003, IEEE Computer Architecture Letters.