A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware

Satisfiability (SAT) is a computationally expensive algorithm central to many CAD and test applications. In this paper, we present the architecture of a new SAT solver using reconfigurable logic. Our main contributions include new forms of massive fine-grain parallelism and structured design techniques based on iterative logic arrays that reduce compilation times from hours to a few minutes. Our architecture is easily scalable. Our results show several orders of magnitude speed-up compared with a state-of-the-art software implementation, and with a prior SAT solver using reconfigurable hardware.

[1]  Sharad Malik,et al.  Certified timing verification and the transition delay of a logic circuit , 1992, DAC '92.

[2]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[3]  Marco Platzner,et al.  Acceleration of Satisfiability Algorithms by Reconfigurable Hardware , 1998, FPL.

[4]  Srinivas Devadas,et al.  Optimal layout via Boolean satisfiability , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[6]  Robert K. Brayton,et al.  Timing analysis and delay-fault test generation using path-recursive functions , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[7]  William H. Mangione-Smith,et al.  Dynamic circuit generation for solving specific problem instances of Boolean satisfiability , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[8]  Daniel G. Saab,et al.  Satisfiability on reconfigurable hardware , 1997, FPL.

[9]  Stephen A. Cook,et al.  The complexity of theorem-proving procedures , 1971, STOC.

[10]  K.A. Sakallah,et al.  Realistic delay modeling in satisfiability-based timing analysis , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[11]  Jun Gu,et al.  Algorithms for the satisfiability (SAT) problem: A survey , 1996, Satisfiability Problem: Theory and Applications.

[12]  Karem A. Sakallah,et al.  GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.

[13]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[14]  José T. de Sousa,et al.  A virtual logic algorithm for solving satisfiability problems using reconfigurable hardware , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[15]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[17]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Rob A. Rutenbar,et al.  Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT , 1999, FPGA '99.

[19]  Jun Gu,et al.  Asynchronous circuit synthesis with Boolean satisfiability , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Sharad Malik,et al.  Accelerating Boolean satisfiability with configurable hardware , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[21]  Panos M. Pardalos,et al.  Satisfiability problem : theory and applications : DIMACS workshop, March 11-13, 1996 , 1997 .

[22]  Sharad Malik,et al.  Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[23]  Makoto Yokoo,et al.  Solving Satisfiability Problems on FPGAs , 1996, FPL.