Mapping Spiking Neural Networks to Neuromorphic Hardware

Neuromorphic hardware implements biological neurons and synapses to execute a spiking neural network (SNN)-based machine learning. We present SpiNeMap, a design methodology to map SNNs to crossbar-based neuromorphic hardware, minimizing spike latency and energy consumption. SpiNeMap operates in two steps: SpiNeCluster and SpiNePlacer. SpiNeCluster is a heuristic-based clustering technique to partition an SNN into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and intercluster global synapses are mapped to the shared interconnect. SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion and improves application performance. SpiNePlacer then finds the best placement of local and global synapses on the hardware using a metaheuristic-based approach to minimize energy consumption and spike latency. We evaluate SpiNeMap using synthetic and realistic SNNs on a state-of-the-art neuromorphic hardware. We show that SpiNeMap reduces average energy consumption by 45% and spike latency by 21%, compared to the best-performing SNN mapping technique.

[1]  Riccardo Poli,et al.  Particle swarm optimization , 1995, Swarm Intelligence.

[2]  Steve B. Furber,et al.  A hierachical configuration system for a massively parallel neural hardware platform , 2012, CF '12.

[3]  Nan Jiang,et al.  A detailed and flexible cycle-accurate Network-on-Chip simulator , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[4]  Nikil D. Dutt,et al.  Unsupervised Heart-rate Estimation in Wearables With Liquid States and A Probabilistic Readout , 2017, Neural Networks.

[5]  Wenguang Chen,et al.  NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[6]  Nikil D. Dutt,et al.  CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters , 2018, 2018 International Joint Conference on Neural Networks (IJCNN).

[7]  Hiroyuki Mori,et al.  Advanced interconnect technologies in the era of cognitive computing , 2016, 2016 Pan Pacific Microelectronics Symposium (Pan Pacific).

[8]  Bernard Brezzo,et al.  TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Andrew S. Cassidy,et al.  Conversion of artificial recurrent neural networks to spiking neural networks for low-power neuromorphic hardware , 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

[10]  Tim Sauer,et al.  Interspike interval embedding of chaotic signals. , 1995, Chaos.

[11]  Salvatore Monteleone,et al.  Noxim: An open, extensible and cycle-accurate network on chip simulator , 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[12]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[13]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[14]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .

[15]  Zhisong Xiao,et al.  Neuromorphic Computing with Memristor Crossbar , 2018 .

[16]  Jun Zhou,et al.  A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips , 2019, ACM Trans. Archit. Code Optim..

[17]  Matthew Cook,et al.  Unsupervised learning of digit recognition using spike-timing-dependent plasticity , 2015, Front. Comput. Neurosci..

[18]  Eris Chinellato,et al.  Facial expression recognition based on Liquid State Machines built of alternative neuron models , 2009, 2009 International Joint Conference on Neural Networks.

[19]  Francky Catthoor,et al.  Mapping of local and global synapses on spiking neuromorphic hardware , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Parami Wijesinghe,et al.  An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain , 2017, IEEE Transactions on Emerging Topics in Computational Intelligence.

[21]  Andrew S. Cassidy,et al.  TrueNorth: Accelerating From Zero to 64 Million Neurons in 10 Years , 2019, Computer.

[22]  Amit Kumar Singh,et al.  Mapping on multi/many-core systems: Survey of current and emerging trends , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[23]  Pietro Perona,et al.  One-shot learning of object categories , 2006, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[24]  Geoff V. Merrett,et al.  Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones , 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[25]  Radu Marculescu,et al.  On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches , 2008, TODE.

[26]  Yiran Chen,et al.  An EDA framework for large scale hybrid neuromorphic computing systems , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[27]  Luis A. Plana,et al.  SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[28]  Kaushik Roy,et al.  SPINDLE: SPINtronic Deep Learning Engine for large-scale neuromorphic computing , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[29]  Guigang Zhang,et al.  Deep Learning , 2016, Int. J. Semantic Comput..

[30]  Amit Kumar Singh,et al.  Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs , 2013, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[31]  Shane Legg,et al.  Human-level control through deep reinforcement learning , 2015, Nature.

[32]  Romain Brette,et al.  Philosophy of the Spike: Rate-Based vs. Spike-Based Theories of the Brain , 2015, Front. Syst. Neurosci..

[33]  P. Debacker,et al.  Design-technology co-optimization for OxRRAM-based synaptic processing unit , 2017, 2017 Symposium on VLSI Technology.

[34]  Geoffrey E. Hinton,et al.  Speech recognition with deep recurrent neural networks , 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

[35]  Henry Markram,et al.  Real-Time Computing Without Stable States: A New Framework for Neural Computation Based on Perturbations , 2002, Neural Computation.

[36]  Rajesh P. N. Rao,et al.  Spike-Timing-Dependent Hebbian Plasticity as Temporal Difference Learning , 2001, Neural Computation.

[37]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[38]  Damien Querlioz,et al.  Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator , 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[39]  Pritish Narayanan,et al.  Neuromorphic computing using non-volatile memory , 2017 .

[40]  Benjamin Schrauwen,et al.  Reservoir-based techniques for speech recognition , 2006, The 2006 IEEE International Joint Conference on Neural Network Proceedings.

[41]  Marc-Oliver Gewaltig,et al.  NEST (NEural Simulation Tool) , 2007, Scholarpedia.

[42]  Romain Brette,et al.  The Brian Simulator , 2009, Front. Neurosci..

[43]  Wofgang Maas,et al.  Networks of spiking neurons: the third generation of neural network models , 1997 .

[44]  Giacomo Indiveri,et al.  A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) , 2017, IEEE Transactions on Biomedical Circuits and Systems.

[45]  Hong Wang,et al.  Loihi: A Neuromorphic Manycore Processor with On-Chip Learning , 2018, IEEE Micro.

[46]  Thomas Nowotny,et al.  GeNN: a code generation framework for accelerated brain simulations , 2016, Scientific Reports.

[47]  Qiang Yang,et al.  Lifelong Machine Learning Systems: Beyond Learning Algorithms , 2013, AAAI Spring Symposium: Lifelong Machine Learning.

[48]  David S. Johnson,et al.  Some simplified polynomial complete problems , 1974 .

[49]  G. Indiveri,et al.  Neuromorphic architectures for spiking deep neural networks , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[50]  Andrew Y. Ng,et al.  Zero-Shot Learning Through Cross-Modal Transfer , 2013, NIPS.

[51]  Russell C. Eberhart,et al.  A new optimizer using particle swarm theory , 1995, MHS'95. Proceedings of the Sixth International Symposium on Micro Machine and Human Science.

[52]  Bharadwaj Veeravalli,et al.  Communication and migration energy aware task mapping for reliable multiprocessor systems , 2014, Future Gener. Comput. Syst..

[53]  Sergey Ioffe,et al.  Rethinking the Inception Architecture for Computer Vision , 2015, 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR).

[54]  Qiang Yang,et al.  A Survey on Transfer Learning , 2010, IEEE Transactions on Knowledge and Data Engineering.

[55]  Deepak Khosla,et al.  Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition , 2014, International Journal of Computer Vision.

[56]  Kaushik Roy,et al.  Neuromorphic Computing Across the Stack: Devices, Circuits and Architectures , 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

[57]  Pierre Yger,et al.  PyNN: A Common Interface for Neuronal Network Simulators , 2008, Front. Neuroinform..

[58]  Francky Catthoor,et al.  Power-Accuracy Trade-Offs for Heartbeat Classification on Neural Networks Hardware , 2018, J. Low Power Electron..

[59]  Francky Catthoor,et al.  Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing , 2019, ACM Great Lakes Symposium on VLSI.

[60]  Joel Emer,et al.  Eyeriss: an Energy-efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks Accessed Terms of Use , 2022 .

[61]  Thomas Brox,et al.  Striving for Simplicity: The All Convolutional Net , 2014, ICLR.

[62]  J. Yang,et al.  Memristive crossbar arrays for brain-inspired computing , 2019, Nature Materials.

[63]  D. P. Phillips,et al.  Separate mechanisms control spike numbers and inter-spike intervals in transient responses of cat auditory cortex neurons , 1991, Hearing Research.

[64]  Y. Dan,et al.  Spike Timing-Dependent Plasticity of Neural Circuits , 2004, Neuron.