Reduction of Computation Delay for Improving Stability and Control Performance of LCL -Type Grid-Connected Inverters

As illustrated in Chap. 8, in the digitally controlled LCL-type grid-connected inverters, proportional feedback of the capacitor current is equivalent to a frequency-dependent virtual impedance connected in parallel with the filter capacitor due to the control delay including the computation and pulse-width modulation (PWM) delays. This virtual impedance leads to the change of the LCL filter resonance frequency. At the frequencies higher than one-sixth of the sampling frequency (f s /6), the virtual impedance contains a negative resistor component. So, if the actual resonance frequency is higher than f s /6, a pair of open-loop right-half-plane (RHP) poles are generated. As a result, the LCL-type grid-connected inverter is easier to be unstable if the resonance frequency is moved closer to f s /6 due to the variation of grid impedance. Meanwhile, the computation and PWM delays also reduce the control bandwidth greatly and thus impose a severe limitation on the low-frequency gains. Therefore, it is desirable to reduce the control delay so as to improve the stability and the control performance of the grid-connected inverter. In this chapter, the influence of the control delay on the LCL-type grid-connected inverter is firstly analyzed. Then, the real-time sampling method [1] and real-time computation method with dual sampling modes [2] are proposed to reduce or even remove the computation delay. Finally, the experimental results from a 6-kW prototype verify the effectiveness of the proposed methods.