Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM

As technology scales down, the sensing margin of spin-transfer-torque random access memory is significantly degraded because of the increased process variation and decreased supply voltage. The sensing current, which is limited to prevent read disturbance, further degrades the sensing margin. To improve the sensing margin, various reference schemes have been proposed. However, it is essential to be selective because the read stability, write ability, and array efficiency are very different according to the reference schemes. This paper presents the study of a variety of reference schemes and outlines five requirements for an optimized reference scheme as follows: 1) no parasitic mismatch, 2) no regularity problem, 3) no read disturbance, 4) no write-current degradation, and 5) small area overhead. A novel reference scheme that satisfies all the requirements for the optimized reference scheme is proposed using four 1T1MTJ cells and a reference word line structure with the same parasitic scheme.

[1]  Seong-Ook Jung,et al.  An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Yiran Chen,et al.  A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme , 2012, IEEE Journal of Solid-State Circuits.

[3]  Seung H. Kang,et al.  A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[4]  John K. DeBrosse,et al.  Design considerations for MRAM , 2006, IBM J. Res. Dev..

[5]  Weisheng Zhao,et al.  High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits , 2009, IEEE Transactions on Magnetics.

[6]  Saied N. Tehrani,et al.  A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects , 2003, IEEE J. Solid State Circuits.

[7]  Chih-Kong Ken Yang,et al.  Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Sreedhar Natarajan,et al.  Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[9]  S. Watts,et al.  Latest Advances and Roadmap for In-Plane and Perpendicular STT-RAM , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[10]  H. Hoenigschmid,et al.  A high-speed 128-kb MRAM core for future universal memory applications , 2004, IEEE Journal of Solid-State Circuits.

[11]  J. Tschanz,et al.  Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances , 2011, IEEE Transactions on Electron Devices.

[12]  Yong Lian,et al.  Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Seong-Ook Jung,et al.  A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Sudhakar Yalamanchili,et al.  A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[16]  Meng-Fan Chang,et al.  A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes , 2013, IEEE Journal of Solid-State Circuits.

[17]  Yoshihiro Ueda,et al.  A 64Mb MRAM with clamped-reference and adequate-reference schemes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[18]  William Song,et al.  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[19]  Doris Schmitt-Landsiedel,et al.  Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[20]  Yiran Chen,et al.  Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  K. Ono,et al.  A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[22]  Hui Zhao,et al.  A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory , 2013, IEEE Journal of Solid-State Circuits.

[23]  H. Ohno,et al.  A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction. , 2010, Nature materials.

[24]  Seong-Ook Jung,et al.  A Split-Path Sensing Circuit for Spin Torque Transfer MRAM , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[25]  J. Otani,et al.  A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[26]  Chih-Kong Ken Yang,et al.  A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs) , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[27]  Shoji Ikeda,et al.  A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme , 2010, IEEE Journal of Solid-State Circuits.

[28]  Hanwool Jeong,et al.  Comparative Study of Various Latch-Type Sense Amplifiers , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Meng-Fan Chang,et al.  An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory , 2013, IEEE Journal of Solid-State Circuits.

[30]  S. Ikeda,et al.  2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read , 2008, IEEE Journal of Solid-State Circuits.

[31]  Y. Suzuki,et al.  Future prospects of MRAM technologies , 2013, 2013 IEEE International Electron Devices Meeting.

[32]  H. Ohno,et al.  Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond , 2010, 2010 IEEE International Memory Workshop.

[33]  Luan Tran,et al.  45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[34]  Chang‐Hwan Choi,et al.  Fabrication of a dense array of tall nanostructures over a large sample area with sidewall profile and tip sharpness control , 2006 .