SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT
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[2] Srinivas Devadas,et al. Optimal layout via Boolean satisfiability , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[3] Stephen A. Cook,et al. The complexity of theorem-proving procedures , 1971, STOC.
[4] J. P. Marques,et al. GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .
[5] Rob A. Rutenbar,et al. Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT , 1999, FPGA '99.
[6] J. Knoch,et al. High-performance carbon nanotube field-effect transistor with tunable polarities , 2005, IEEE Transactions on Nanotechnology.
[7] Giovanni De Micheli,et al. An Efficient Gate Library for Ambipolar CNTFET Logic , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] N. Yokoyama,et al. A polarity-controllable graphene inverter , 2010 .
[9] Davide Pandini,et al. Maximization of layout printability/manufacturability by extreme layout regularity , 2007 .
[10] Nikolai Ryzhenko,et al. Standard cell routing via Boolean satisfiability , 2012, DAC Design Automation Conference 2012.
[11] Toby Walsh,et al. Handbook of satisfiability , 2009 .
[12] C. Hu,et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .
[13] G. De Micheli,et al. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.
[14] Suhas N. Yadav,et al. MULTIPLE GATE FIELD-EFFECT TRANSISTORS FOR FUTURE CMOS TECHNOLOGIES , 2014 .
[15] Yusuf Leblebici,et al. Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors , 2012, DAC Design Automation Conference 2012.
[16] Giovanni De Micheli,et al. MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).