Exploring the potential of context-aware dynamic CPU undervolting

CPU operation at sub-nominal voltage levels has been researched to reduce the power and energy consumption of computer systems. While it is possible to determine a safe undervolting level for each application, typically only the most conservative setting is applied statically across all workloads. In this paper, we go a step further and investigate the gains that can be achieved by dynamically and transparently changing the level of CPU undervolting at runtime. To enable this functionality, we design and implement a novel, OS-level, context-aware dynamic undervolting mechanism, able to decide and apply voltage levels according to the specific tolerance of each workload that executes on a multicore CPU at a particular time. Our mechanism can further differentiate between the user- and kernel-level code executed within the same application thread, enabling the exploitation of differences in their undervolting potential. User- and kernel-level code have inherently different characteristics, yet in previous work have never been characterized individually. Our experiments, on an Intel x86-64 multicore show that the proposed approach can reduce the average CPU power consumption by 5.58%/30.05% compared to static undervolting and the nominal voltage level, respectively. Finally, we provide indicative estimates for the gains that could be achieved in future CPU architectures with multiple, per-core voltage domains.

[1]  Osman S. Unsal,et al.  Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies , 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

[2]  Puneet Gupta,et al.  Variability-aware memory management for nanoscale computing , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[3]  Shuaiwen Song,et al.  Investigating the Interplay between Energy Efficiency and Resilience in High Performance Computing , 2015, 2015 IEEE International Parallel and Distributed Processing Symposium.

[4]  Zizhong Chen,et al.  GreenMM: energy efficient GPU matrix multiplication through undervolting , 2019, ICS.

[5]  Dimitris Gizopoulos,et al.  Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs , 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[6]  Lars C. Wolf,et al.  IdealVolting: Reliable Undervolting on Wireless Sensor Nodes , 2016, TOSN.

[7]  Jingwen Leng,et al.  Adaptive guardband scheduling to improve system-level efficiency of the POWER7+ , 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Ravishankar K. Iyer,et al.  Effectiveness of machine checks for error diagnostics , 2009, 2009 IEEE/IFIP International Conference on Dependable Systems & Networks.

[9]  John L. Henning.  SPEC CPU2006 benchmark descriptions , 2006, CARN.

[10]  Jingwen Leng,et al.  Energy Efficiency Benefits of Reducing the Voltage Guardband on the Kepler GPU Architecture , 2014 .

[11]  A. Kivity,et al.  kvm : the Linux Virtual Machine Monitor , 2007 .

[12]  Ilia Polian,et al.  Adaptive voltage over-scaling for resilient applications , 2011, 2011 Design, Automation & Test in Europe.

[13]  Panos K. Koutsovasilis,et al.  The Impact of CPU Voltage Margins on Power-Constrained Execution , 2020, IEEE Transactions on Sustainable Computing.

[14]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[15]  Osman S. Unsal,et al.  Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories , 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[16]  Eric Cheng,et al.  Very Low Voltage (VLV) Design , 2017, 2017 IEEE International Conference on Computer Design (ICCD).

[17]  Dimitris Gizopoulos,et al.  Voltage margins identification on commercial x86-64 multicore microprocessors , 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

[18]  Spyros Lalis,et al.  Exploiting CPU Voltage Margins to Increase the Profit of Cloud Infrastructure Providers , 2019, 2019 19th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGRID).

[19]  Pradip Bose,et al.  Safe limits on voltage reduction efficiency in GPUs: A direct measurement approach , 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[20]  Laurent Lefèvre,et al.  Application-Agnostic Framework for Improving the Energy Efficiency of Multiple HPC Subsystems , 2015, 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

[21]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[22]  Fabrice Bellard,et al.  QEMU, a Fast and Portable Dynamic Translator , 2005, USENIX ATC, FREENIX Track.

[23]  Meeta Sharma Gupta,et al.  Voltage emergency prediction: Using signatures to reduce operating margins , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[24]  Pradip Bose,et al.  BRAVO: Balanced Reliability-Aware Voltage Optimization , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[25]  Sujit Dey,et al.  Variation-Tolerant Dynamic Power Management at the System-Level , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Hamid Sarbazi-Azad,et al.  Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling , 2020, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[27]  Radu Teodorescu,et al.  Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors , 2013, ISCA.

[28]  Jun Liu,et al.  Energy efficient scheduling of real-time tasks on multi-core processors with voltage islands , 2016, Future Gener. Comput. Syst..

[29]  Massimo Alioto,et al.  Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore’s Law , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[30]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[31]  Shidhartha Das,et al.  Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs , 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[32]  Spyros Lalis,et al.  Significance-Aware Program Execution on Unreliable Hardware , 2017, ACM Trans. Archit. Code Optim..

[33]  Shidhartha Das,et al.  An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[34]  Shuaiwen Song,et al.  Combating the reliability challenge of GPU register file at low supply voltage , 2016, 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT).

[35]  Bishop Brock,et al.  Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[36]  Shidhartha Das,et al.  Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs , 2018, 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).

[37]  Yijia Zhang,et al.  An empirical survey of performance and energy efficiency variation on Intel processors , 2017, E2SC@SC.

[38]  Li Zhou,et al.  Core tunneling: Variation-aware voltage noise mitigation in GPUs , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[39]  Lara Dolecek,et al.  Underdesigned and Opportunistic Computing in Presence of Hardware Variability , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[40]  Spyros Lalis,et al.  Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs , 2020, IEEE Transactions on Parallel and Distributed Systems.

[41]  Roberto Giorgio Rizzo,et al.  Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling , 2017, 2017 New Generation of CAS (NGCAS).

[42]  Jan Reineke,et al.  nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems , 2019, 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[43]  Radu Teodorescu,et al.  Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[44]  Mehdi B. Tahoori,et al.  Runtime Adjustment of IoT System-on-Chips for Minimum Energy Operation , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).