Low power, high speed, charge recycling CMOS threshold logic gate

A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.

[1]  Tadashi Shibata,et al.  Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[2]  Hong-Yi Huang,et al.  CMOS capacitor coupling logic (C/sup 3/L) circuits , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[3]  Saburo Muroga,et al.  Threshold logic and its applications , 1971 .

[4]  Maria J. Avedillo,et al.  Low-power CMOS threshold-logic gate , 1995 .

[5]  Bai-Sun Kong,et al.  Asynchronous sense differential logic , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[6]  P. Guillon,et al.  Dielectric resonators , 1988, Proceedings of the 42nd Annual Frequency Control Symposium, 1988..