Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-volatile memory which can be embedded into standard CMOS process. A wide range of write speeds from 1ns to 100ns have been reported for STT-RAM. The switching current of magnetic tunnel junction (MTJ) (which is the storage element of STT-RAM) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We take the typical in-plane MTJ and advanced perpendicular MTJ (PMTJ) as our optimization targets. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that “sweet spots” of write pulse width which minimize the write energy or write latency of STT-RAM caches may exist. The optimal write pulse width depends on MTJ specifications, STT-RAM capacity and I/O width. The simulation results indicate that by utilizing PMTJ, the optimized STT-RAM can compete against SRAM and DRAM as universal memory replacement in low power embedded systems.1

[1]  H. Meng,et al.  Spin transfer in nanomagnetic devices with perpendicular anisotropy , 2006 .

[2]  Yiran Chen,et al.  Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[3]  Z. Diao,et al.  Spin transfer switching and spin polarization in magnetic tunnel junctions with MgO and AlOx barriers , 2005, cond-mat/0510204.

[4]  S. Watts,et al.  Latest Advances and Roadmap for In-Plane and Perpendicular STT-RAM , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[5]  Mircea R. Stan,et al.  FlashPower: A detailed power model for NAND flash memory , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[6]  Z. Diao,et al.  Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory , 2007 .

[7]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[8]  Sudhakar Yalamanchili,et al.  A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  S. Takahashi,et al.  Lower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM , 2008, 2008 IEEE International Electron Devices Meeting.

[10]  Ilya Krivorotov,et al.  Switching current reduction using perpendicular anisotropy in CoFeB-MgO magnetic tunnel junctions , 2011 .

[11]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[12]  A. Natarajarathinam,et al.  Perpendicular Magnetic Tunnel Junctions Using Co-based Multilayers , 2010 .

[13]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[14]  Patrick Ndai,et al.  Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Cong Xu,et al.  Design implications of memristor-based RRAM cross-point structures , 2011, 2011 Design, Automation & Test in Europe.

[16]  Yuan Xie,et al.  PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[17]  J. Slonczewski Currents, torques, and polarization factors in magnetic tunnel junctions , 2004, cond-mat/0404210.

[18]  Arijit Raychowdhury,et al.  Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[19]  Jaejin Lee,et al.  FaCSim: a fast and cycle-accurate architecture simulator for embedded systems , 2008, LCTES '08.

[20]  L. Tran,et al.  A 78nm 6F DRAM Technology for Multigigabit Densities , 2004 .

[21]  Luan Tran,et al.  45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[22]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[23]  L. Tran,et al.  A 78nm 6F/sup 2/ DRAM technology for multigigabit densities , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[24]  Z. Diao,et al.  Spin transfer switching in dual MgO magnetic tunnel junctions , 2007 .

[25]  Yiran Chen,et al.  Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM) , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Mircea R. Stan,et al.  The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory , 2010, Proceedings of the IEEE.

[27]  Mircea R. Stan,et al.  Relaxing non-volatility for fast and energy-efficient STT-RAM caches , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[28]  Mircea R. Stan,et al.  Advances and Future Prospects of Spin-Transfer Torque Random Access Memory , 2010, IEEE Transactions on Magnetics.

[29]  J. Zhu,et al.  Spin Torque and Field-Driven Perpendicular MRAM Designs Scalable to Multi-Gb/Chip Capacity , 2006, IEEE Transactions on Magnetics.