A BDD-Based Design of an Area-Power Efficient Asynchronous Adder

Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. On the other hand Binary Decision Diagrams (BDDs) have found significant applications for many years in the design, synthesis, verification, and testing of VLSI circuits. In this paper we have presented the design of a hybrid Domino PTL-CMOS based 2-bit asynchronous adder, the PTL part of which is designed using the principles of BDD. The designed asynchronous adder has been implemented for 32-bit and the simulation results indicate a reduction of 16% in number of transistors, 8% in power and 21% in power-delay-area-product over earlier reported results without any compromise in the delay. The implementation has been done using UMC 180nm, 1.5V technology.

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