Delay optimization of combinational logic circuits by clustering and partial collapsing

The authors propose a novel technology-independent algorithm to minimize circuit delay. The algorithm works in two steps. The first step performs a partial collapse of the circuit based on a delay-driven clustering. The second step factorizes and simplifies the circuit without increasing the number of levels of logic. The computational cost of the algorithm is dominated by the simplification step. To estimate circuit delay, a state-of-the-art technology mapper is used, incorporating fanout optimization and tree covering for delay minimization. On average over a representative set of benchmarks, a delay reduction of 18% is obtained for an area increase of 11%.<<ETX>>