On Functional Broadside Tests With Functional Propagation Conditions

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the second capture cycle. As a result, a functional broadside test may detect faults that cannot affect functional operation (redundant faults). Addressing this issue completely requires full sequential test generation. We discuss an alternate solution that fits naturally with an existing process for generating functional broadside tests.

[1]  Saburo Muroga,et al.  Binary Decision Diagrams , 2000, The VLSI Handbook.

[2]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Irith Pomeranz,et al.  On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic , 2003, ICCAD 2003.

[4]  Irith Pomeranz,et al.  Generation of Functional Broadside Tests for Transition Faults , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Michael S. Hsiao,et al.  A Study of Implication Based Pseudo Functional Testing , 2006, 2006 IEEE International Test Conference.

[6]  Irith Pomeranz,et al.  On Complete Functional Broadside Tests for Transition Faults , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Minesh B. Amin,et al.  Efficient compression and application of deterministic patterns in a logic BIST architecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[8]  Irith Pomeranz,et al.  Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Irith Pomeranz,et al.  Scan tests with multiple fault activation cycles for delay faults , 2006, 24th IEEE VLSI Test Symposium.

[10]  Spyros Tragoudas,et al.  On the Use of Counters for Reproducing Deterministic Test Sets , 1996, IEEE Trans. Computers.

[11]  Albrecht P. Stroele,et al.  BIST Pattern Generators Using Addition and Subtraction Operations , 1997, J. Electron. Test..

[12]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[13]  Sreejit Chakravarty,et al.  An Approach to Minimizing Functional Constraints , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[14]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[15]  Jeff Rearick Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Daniel Brand,et al.  Identification of redundant delay faults , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Salvador Manich,et al.  Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Michael S. Hsiao,et al.  Constrained ATPG for broadside transition testing , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[19]  Irith Pomeranz,et al.  A test generation procedure for avoiding the detection of functionally redundant transition faults , 2006, 24th IEEE VLSI Test Symposium.

[20]  Irith Pomeranz,et al.  Forward-looking fault simulation for improved static compaction , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Albrecht P. Stroele,et al.  Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes , 2000, J. Electron. Test..

[22]  Irith Pomeranz,et al.  PROPTEST: a property-based test generator for synchronous sequential circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[24]  I. Voyiatzis,et al.  Accumulator - based compression in symmetric transparent RAM BIST , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

[25]  Irith Pomeranz On the generation of scan-based test sets with reachable states for testing under functional operation conditions , 2004, Proceedings. 41st Design Automation Conference, 2004..

[26]  Feng Lu,et al.  Constraint extraction for pseudo-functional scan-based delay testing , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[27]  Irith Pomeranz,et al.  On generating pseudo-functional delay fault tests for scan designs , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[28]  Ahmad A. Al-Yamani,et al.  Seed encoding with LFSRs and cellular automata , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[29]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..