Design-specific path delay testing in lookup-table-based FPGAs
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[1] Charles E. Stroud,et al. Built-in self-test of FPGA interconnect , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[2] Russell Tessier,et al. Testing and diagnosis of interconnect faults in cluster-based FPGA architectures , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Erik Chmelar,et al. FPGA Interconnect Delay Fault Testing , 2003, ITC.
[4] Shyue-Kung Lu,et al. Testing Configurable LUT-Based FPGAs , 2000, J. Inf. Sci. Eng..
[5] Fabrizio Lombardi,et al. Testing configurable LUT-based FPGA's , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[6] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[7] Slawomir Pilarski,et al. BIST and delay fault detection , 1993, Proceedings of IEEE International Test Conference - (ITC).
[8] E. Chmelaf. Fpga interconnect delay fault testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[9] Mehdi B. Tahoori,et al. Interconnect delay testings of designs on programmable logic devices , 2004 .
[10] Sandeep K. Gupta,et al. Design of efficient BIST test pattern generators for delay testing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Premachandran R. Menon,et al. BIST-based delay path testing in FPGA architectures , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[12] Charles E. Stroud,et al. Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[13] Fabrizio Lombardi,et al. IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays , 1998, IEEE Trans. Computers.
[14] Andrzej Krasniewski. Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices , 2003, FPL.
[15] Spyros Tragoudas,et al. Efficient identification of (critical) testable path delay faults using decision diagrams , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Edward J. McCluskey,et al. Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.
[17] Charles E. Stroud,et al. BIST-Based Delay-Fault Testing in FPGAs , 2003, J. Electron. Test..
[18] Ping Chen,et al. Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.
[19] Russell Tessier,et al. Adaptive fault recovery for networked reconfigurable systems , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..
[20] Andrzej Krasniewski. Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs , 2003, J. Syst. Archit..
[21] Andrzej Krasniewski. Application-dependent testing of FPGA delay faults , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.
[22] Russell Tessier,et al. Interconnect testing in cluster-based FPGA architectures , 2000, Proceedings 37th Design Automation Conference.
[23] M. Ray Mercer,et al. An efficient delay test generation system for combinational logic circuits , 1991, DAC '90.
[24] Yervant Zorian,et al. Test of RAM-based FPGA: methodology and application to the interconnect , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[25] Andrzej Krasniewski. Enhancing Detection of Delay Faults in FPGA-Based Circuits by Transformations of LUT Functions , 2000 .
[26] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[27] M. Ray Mercer,et al. An efficient delay test generation system for combinational logic circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[28] Patrick Girard,et al. Defect analysis for delay-fault BIST in FPGAs , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..
[29] Andrzej Krasniewski. Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs , 2000, FPL.
[30] Charles E. Stroud,et al. Online BIST and BIST-based diagnosis of FPGA logic blocks , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[31] Victor Lee,et al. The RAW benchmark suite: computation structures for general purpose computing , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).