Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications

OpenCL for FPGAs has emerged as an attractive solution for realizing massively parallel compute-intensive applications. It offers a customizable application-specific datapath while abstracting away hardware development complexity. Research on OpenCL for FPGAs is at early stages and many aspects such as the spatial parallelism matching with respect to OpenCL execution semantic has not been explored in detail. An in-depth understanding and formalization are required to enhance the efficiency of OpenCL written codes on FPGAs and improve the parallelism potentials to the fullest. This paper presents a comprehensive study to identify, analyze and categorize the spatial parallelism when mapping OpenCL kernels to the FPGAs. The paper studies and explores the impact of Data-Path (DP) replication and Compute Unit (CU) replication on performance and power efficiency of OpenCL execution on FPGAs. To this end, this paper proposes a generic taxonomy for classifying spatial parallelism when mapping OpenCL to FPGAs. This results in developing FPGA-aware OpenCL codes that can achieve much higher efficiency over a baseline implementation. Our experimental results on Altera Stratix-V FPGA device for eight applications of Rodinia benchmarks demonstrate that FPGA-aware OpenCL codes achieve 3.4X, 2.2X and 2.6X performance improvement on average for SCU-MDP, MCU-SDP, and MCU-MDP versions over SCU-SDP as the baseline implementation. Furthermore, we compare the performance and power efficiency against AMD FirePro W7100 GPU. Our results demonstrate that benchmarks with regular execution patterns can outperform GPUs, achieving much higher performance per watt. Furthermore, OpenCL source-code decisions that can exploit spatial parallelism will be able to hide the memory access latency and thus result in a higher speedup.

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