BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research

Heterogeneous architectures and heterogeneous-ISA designs are growing areas of computer architecture and system software research. Unfortunately, this line of research is significantly hindered by the lack of experimental systems and modifiable hardware frameworks. This work proposes BYOC, a "Bring Your Own Core" framework that is specifically designed to enable heterogeneous-ISA and heterogeneous system research. BYOC is an open-source hardware framework that provides a scalable cache coherence system, that includes out-of-the-box support for four different ISAs (RISC-V 32-bit, RISC-V 64-bit, x86, and SPARCv9) and has been connected to ten different cores. The framework also supports multiple loosely coupled accelerators and is a fully working system supporting SMP Linux. The Transaction-Response Interface (TRI) introduced with BYOC has been specifically designed to make it easy to add in new cores with new ISAs and memory interfaces. This work demonstrates multiple multi-ISA designs running on FPGA and characterises the communication costs. This work describes many of the architectural design trade-offs for building such a flexible system. BYOC is well suited to be the premiere platform for heterogeneous-ISA architecture, system software, and compiler research.

[1]  Luca Benini,et al.  HERO: an open-source research platform for HW/SW exploration of heterogeneous manycore systems , 2018, ANDARE '18.

[2]  David Wentzlaff,et al.  JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores , 2019, FPGA.

[3]  Zhen Wang,et al.  K2 , 2015, False Summit.

[4]  David H. Ackley,et al.  Randomized instruction set emulation to disrupt binary code injection attacks , 2003, CCS '03.

[5]  Christopher Batten,et al.  PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[6]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[7]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[8]  Luca P. Carloni,et al.  Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip , 2016, 2016 International Conference on Compliers, Architectures, and Sythesis of Embedded Systems (CASES).

[9]  Luca P. Carloni,et al.  An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[10]  Hovav Shacham,et al.  HIPStR: Heterogeneous-ISA Program State Relocation , 2016, ASPLOS.

[11]  Eric Rotenberg,et al.  AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores , 2016, 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[12]  Dean M. Tullsen,et al.  Execution migration in a heterogeneous-ISA chip multiprocessor , 2012, ASPLOS XVII.

[13]  Luca P. Carloni,et al.  NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators , 2018, 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[14]  David Wentzlaff,et al.  OpenPiton: An Open Source Manycore Research Framework , 2016, ASPLOS.

[15]  David Wentzlaff,et al.  Coherence domain restriction on large scale systems , 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[16]  Christopher Torng,et al.  The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips , 2018, IEEE Micro.

[17]  Gavin Ferris,et al.  Tagged memory and minion cores in the lowRISC SoC , 2014 .

[18]  Ramón Beivide,et al.  Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip , 2019, ISUM.

[19]  Eric Rotenberg,et al.  AnyCore-1: A comprehensively adaptive 4-way superscalar processor , 2016, 2016 IEEE Hot Chips 28 Symposium (HCS).

[20]  Dean M. Tullsen,et al.  Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures , 2019, PMAM@PPoPP.

[21]  Michael Bedford Taylor,et al.  INVITED: BaseJump STL: SystemVerilog Needs a Standard Template Library for Hardware Design , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[22]  Jonathan Balkind,et al.  OpenPiton + Ariane : The First Open-Source , SMP Linux-booting RISC-V System Scaling From One to Many Cores , 2019 .

[23]  Dean M. Tullsen,et al.  Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA , 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[24]  Mark D. Hill,et al.  Accelerator-level parallelism , 2019, Commun. ACM.

[25]  Sarita V. Adve,et al.  Spandex: A Flexible Interface for Efficient Heterogeneous Coherence , 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

[26]  木村 康則,et al.  Gordon E. Moore : Cramming More Components onto Integrated Circuits(20世紀の名著名論) , 2005 .

[27]  Karthikeyan Sankaralingam,et al.  MIAOW - An open source RTL implementation of a GPGPU , 2015, 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII).

[28]  Simha Sethumadhavan,et al.  Reviving instruction set randomization , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[29]  Dean M. Tullsen,et al.  Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[30]  Michael Bedford Taylor,et al.  Basejump STL: systemverilog needs a standard template library for hardware design , 2018, DAC.

[31]  Rangeen Basu Roy Chowdhury.  AnyCore: Design, Fabrication, and Evaluation of Comprehensively Adaptive Superscalar Processors , 2016 .

[32]  David A. Wood,et al.  Crossing Guard: Mediating Host-Accelerator Coherence Interactions , 2017, ASPLOS.

[33]  Luca Benini,et al.  The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Norman P. Jouppi,et al.  Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction , 2003, MICRO.

[35]  Binoy Ravindran,et al.  Harnessing Energy Efficiency of Heterogeneous-ISA Platforms , 2015, OPSR.

[36]  David Wentzlaff,et al.  MITTS: Memory Inter-arrival Time Traffic Shaping , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[37]  David Wentzlaff,et al.  Power and Energy Characterization of an Open Source 25-Core Manycore Processor , 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[38]  B. Ravindran,et al.  Operating System Process and Thread Migration in Heterogeneous Platforms , 2016 .