Hardware Evolution with a Massively Parallel Dynamically Reconfigurable Computer: POLYP

POLYP is a second generation, massively parallel reconfigurable computer based on micro-reconfigurable Field Programmable Gate Arrays (Xilinx XC6000) with a high density of additional distributed memory under local control and broad-band dynamically reroutable optical interconnect technology. Inspired by and designed to study the dynamical self-organization of distributed molecular biological systems using the programmable matter paradigm (like its predecessor NGEN), the new hardware allows the study of large interacting evolving populations of functional design elements in hardware. POLYP includes 144 FPGAs and 400 MB of high speed distributed memory on twelve 18-layer extended VME boards each interconnected via 2 crossbars to 80 unidirectional optical fibers. It is extendable to 20 boards in a single chassis and further to asynchronous multiple host operation. Local reconfiguration of the hardware is mediated by an intermediate hierarchical level of distributed macro-reconfigurable FPGAs, so that the machine is capable of simultaneously evolving functional circuits and their binary representation under user-configurable local control. The process of hierarchical configuration reached the fine-grained level in November 1997, and this paper reports a first experiment in hardware evolution performed with the machine. In contrast with previous evolvable hardware examples, the example is designed to explore the evolution of interconnection structures. As a first step with the new hardware, it by no means yet exploits the powerful potential of the machine. Just as NGEN allowed the study of spatially distributed epigenetic effects in interacting populations of molecules in user-configurable hardware, POLYP allows the study of such effects with individuals dynamically reconfiguring the local hardware.