Large Capacity Cache Design Based on Emerging Non-Volatile Memory

A triple-level-cell (TLC) STT-RAM architecture was proposed basing on parallel MLC MTJ and serial MLC MTJ. A TLC STT-RAM cell can store three bit which will offer higher capacity density compared with SLC STT-RAM. The write process is also analyzed that it contains three types of basic states transitions. Through mapping soft, medium and hard domains to three individual cache lines, the access to soft lines can perform as accessing SLC STT-RAM-based cache. The amount of three-step operations is also much reduced. .

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