Effective Logic Synthesis for Threshold Logic Circuit Design

This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches.

[1]  Peichen Pan,et al.  A new retiming-based technology mapping algorithm for LUT-based FPGAs , 1998, FPGA '98.

[2]  Chun-Yao Wang,et al.  On rewiring and simplification for canonicity in threshold logic circuits , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[4]  Meghanad D. Wagh,et al.  Decomposition of threshold functions into bounded fan-in threshold functions , 2013, Inf. Comput..

[5]  Robert K. Brayton,et al.  Improvements to Technology Mapping for LUT-Based FPGAs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Spyros Tragoudas,et al.  Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms , 2014, ACM J. Emerg. Technol. Comput. Syst..

[7]  Alan Mishchenko,et al.  Threshold logic synthesis based on cut pruning , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Sarma B. K. Vrudhula,et al.  Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture , 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[9]  Alan Mishchenko,et al.  Dataset for: Effective Logic Synthesis Flow for Threshold Logic Circuit Design , 2017 .

[10]  Seyed Nima Mozaffari,et al.  A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Sungmin Cho,et al.  Combinational and sequential mapping with priority cuts , 2007, ICCAD 2007.

[12]  Deliang Fan,et al.  Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices , 2017, IEEE Transactions on Emerging Topics in Computing.

[13]  Yung-Chih Chen,et al.  Rewiring for threshold logic circuit minimization , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Leonardo Franco,et al.  A New Decomposition Algorithm for Threshold Synthesis and Generalization of Boolean Functions , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Niraj K. Jha,et al.  Threshold network synthesis and optimization and its application to nanotechnologies , 2005 .

[17]  Mayler G. A. Martins,et al.  Functional composition: A new paradigm for performing logic synthesis , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[18]  Reiner Kolla,et al.  Boolean matching for large libraries , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[19]  Sarma B. K. Vrudhula,et al.  Identification of Threshold Functions and Synthesis of Threshold Networks , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Mayler G. A. Martins,et al.  A Simple and Effective Heuristic Method for Threshold Logic Identification , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  D. B. Strukov,et al.  Programmable CMOS/Memristor Threshold Logic , 2013, IEEE Transactions on Nanotechnology.

[22]  Yung-Chih Chen,et al.  Fast synthesis of threshold logic networks with optimization , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[23]  Sarma B. K. Vrudhula,et al.  Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Mayler G. A. Martins,et al.  Synthesis of threshold logic gates to nanoelectronics , 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

[25]  R. Brayton,et al.  Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs , 2007 .

[26]  Sarma B. K. Vrudhula,et al.  Design of threshold logic gates using emerging devices , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[27]  M. Avedillo,et al.  Improved Nanopipelined RTD Adder Using Generalized Threshold Gates , 2011, IEEE Transactions on Nanotechnology.

[28]  Alex Pappachen James,et al.  A Survey of Memristive Threshold Logic Circuits , 2016, IEEE Transactions on Neural Networks and Learning Systems.

[29]  Sarma B. K. Vrudhula,et al.  Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks , 2016, ArXiv.

[30]  Saburo Muroga,et al.  Threshold logic and its applications , 1971 .

[31]  Mayler G. A. Martins,et al.  A constructive approach for threshold logic circuit synthesis , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[32]  Valeriu Beiu,et al.  VLSI implementations of threshold logic-a comprehensive survey , 2003, IEEE Trans. Neural Networks.

[33]  Spyros Tragoudas,et al.  Maximum weighted independent sets on transitive graphs and applications1 , 1999, Integr..