Closing the power gap between ASIC and custom: an ASIC perspective

We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6/spl mu/m to 0.13/spl mu/m CMOS. A variety of factors cause synthesizable designs to consume /spl times/3 to /spl times/7 more power. We discuss the shortcomings of typical synthesis flows, and changes to tools and standard cell libraries needed to reduce power. Using these methods, we believe that the power gap between ASICs and custom circuits can be closed to within /spl times/2.

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