A Field-Programmable Gate-Array System for Evolutionary Computation

In evolutionary computation, evolutionary operations are applied to a large number of individuals (genes) repeatedly. The computation can be pipelined (evolutionary operators) and parallelized (a large number of individuals) by dedicated hardwares, and high performance are expected. However, details of the operators depend on given problems and vary considerably. Systems with field programmable gate arrays can be reconfigured and realize the most suitable circuits for given problems. In this paper, we show that a hardware system with two FPGAs and SRAMs can achieve 50∼130 times of speedup compared with a workstation (200MHz) in some evolutionary computation problems. With a larger system, we believe that we can realize more than 10 thousands of speedup.