Power regulation in high performance multicore processors

This paper presents, implements, and evaluates a power-regulation technique for multicore processors, based on an integral controller with adjustable gain. The gain is designed for wide stability margins, and computed in real time as part of the control law. The tracking performance of the control system is robust with respect to modeling uncertainties and computational errors in the loop. The main challenge of designing such a controller is that the power dissipation of program-workloads varies widely and often cannot be measured accurately; hence extant controllers are either ad hoc or based on a-priori modeling characterizations of the processor and workloads. Our approach is different. Leveraging the aforementioned robustness it uses a simple textbook modeling framework, and adjusts its parameters in real time by a system-identification module. In this it trades modeling precision for fast computations in the loop making it suitable for on-line implementation in commodity data-center processors. Consequently, the proposed controller is agnostic in the sense that it does not require apriori system characterizations. We present an implementation of the controller on Intel's fourth-generation microarchitecture, Haswell, and test it on industry benchmark programs which are used in datacenter applications. Results of these experiments are presented in detail exposing some practical challenges of implementing provably-convergent power regulation solutions in commodity multicore processors.

[1]  Vanish Talwar,et al.  No "power" struggles: coordinated multi-level power management for the data center , 2008, ASPLOS.

[2]  Jack J. Dongarra,et al.  A Portable Programming Interface for Performance Evaluation on Modern Processors , 2000, Int. J. High Perform. Comput. Appl..

[3]  Christos G. Cassandras,et al.  Introduction to Discrete Event Systems , 1999, The Kluwer International Series on Discrete Event Dynamic Systems.

[4]  Venkatram Krishnaswamy,et al.  4.3 Fine-grained adaptive power management of the SPARC M7 processor , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[5]  Sudhakar Yalamanchili,et al.  Throughput regulation in multicore processors via IPA , 2012, 2012 IEEE 51st IEEE Conference on Decision and Control (CDC).

[6]  Peter Lancaster,et al.  Error analysis for the Newton-Raphson method , 1966 .

[7]  Michael Kistler,et al.  The case for power management in web servers , 2002 .

[8]  Stéphan Jourdan,et al.  Haswell: The Fourth-Generation Intel Core Processor , 2014, IEEE Micro.

[9]  Arun K. Somani,et al.  Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors , 2016, IEEE Transactions on Computers.

[10]  Xi-Ren Cao,et al.  Perturbation analysis of discrete event dynamic systems , 1991 .

[11]  Ching-Yung Lin,et al.  GraphBIG: understanding graph computing in the context of industrial solutions , 2015, SC15: International Conference for High Performance Computing, Networking, Storage and Analysis.

[12]  Avinash Ananthakrishnan,et al.  Power management on 14 nm Intel® Core− M processor , 2015, 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII).

[13]  Eun Jung Kim,et al.  Predictive dynamic thermal management for multicore systems , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[14]  Michael C. Caramanis,et al.  Real-time power control of data centers for providing Regulation Service , 2013, 52nd IEEE Conference on Decision and Control.

[15]  Karel J. Keesman,et al.  System Identification: An Introduction , 2011 .

[16]  Mahmut T. Kandemir,et al.  CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

[17]  Se Won Kim,et al.  Workload prediction using run-length encoding for runtime processor power management , 2015 .

[18]  Carla Seatzu,et al.  Performance Regulation Via Integral Control in a Class of Stochastic Discrete Event Dynamic Systems , 2014, WODES.

[19]  Guanglei Liu,et al.  Neighbor-aware dynamic thermal management for multi-core platform , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[21]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[22]  Kai Ma,et al.  Adaptive Power Control with Online Model Estimation for Chip Multiprocessors , 2011, IEEE Transactions on Parallel and Distributed Systems.

[23]  Gene F. Franklin,et al.  Feedback Control of Dynamic Systems , 1986 .

[24]  Xiaorui Wang,et al.  Power capping: a prelude to power shifting , 2008, Cluster Computing.

[25]  Sudhakar Yalamanchili,et al.  IPA in the loop: Control design for throughput regulation in computer processors , 2016, 2016 13th International Workshop on Discrete Event Systems (WODES).

[26]  Sudhakar Yalamanchili,et al.  Throughput Regulation in Shared Memory Multicore Processors , 2015, 2015 IEEE 22nd International Conference on High Performance Computing (HiPC).

[27]  Sudhakar Yalamanchili,et al.  A power capping controller for multicore processors , 2012, 2012 American Control Conference (ACC).

[28]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .