论文信息 - An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation

An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation

We present a massively parallel VLSI realisation of a pulse-coupled neural network for image segmentation. The network consists of simple integrate-and-fire (IAF) neurons with self-organising local connections. The prototype implementation comprises 64 x 64 neurons with coupling of four nearest neighbours, digital to analog converters, analog memories and a digital readout circuit. The chip has been fabricated in a 0.35μm standard CMOS technology.

S. Getzlaff | D. Matolin | S. Schreiter | S. Schuffny

[1] Bogdan M. Wilamowski,et al. Analog implementation of pulse-coupled neural networks , 1999, IEEE Trans. Neural Networks.

[2] Ulrich Ramacher,et al. Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity , 2002, Proceedings of the 12th IEEE Workshop on Neural Networks for Signal Processing.

[3] Eugene M. Izhikevich,et al. Weakly pulse-coupled oscillators, FM interactions, synchronization, and oscillatory associative memory , 1999, IEEE Trans. Neural Networks.

[4] D. Hubel,et al. Receptive fields, binocular interaction and functional architecture in the cat's visual cortex , 1962, The Journal of physiology.

[5] Giacomo Indiveri,et al. Modeling Selective Attention Using a Neuromorphic Analog VLSI Device , 2000, Neural Computation.

[6] Vittorio Dante,et al. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory , 2003, IEEE Trans. Neural Networks.

[7] Carver Mead,et al. Analog VLSI and neural systems , 1989 .

[8] Ernst Niebur,et al. A Competitive Network of Spiking VLSI Neurons , 2001 .

[9] Christoph von der Malsburg,et al. The Correlation Theory of Brain Function , 1994 .

[10] Russell Beale,et al. Handbook of Neural Computation , 1996 .