The Need for Formal Methods for Integrated Circuit Design

This paper has reviewed the typical rt1 and behavioral synthesis design flows and identified areas where formal methods can be applied. In particular, the problems of design and implementation verification were identified as amenable to formal techniques and a number of well-motivated areas for research were identified. These included: Formalisms to discipline human reasoning during the generation of an rt1 or behavioral-level design; Formal semantics for synthesizable subsets of existing hardware-design languages such as VHDL and Verilog; Formal methods for specification which are intuitive and easy to use; Formal means for expressing properties of integrated circuits; Formal methods for verifying properties of integrated circuits; Formal methods for verifying that an rt1 representation is consistent with a behavioral-level representation; More robust methods for verifying that two sequential circuits are equivalent.

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