Efficient generation of test patterns using Boolean satisfiability

A combinational circuit can be tested for the presence of a single stuck-at fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of an automatic test pattern generating system is to generate a set of input sets that will detect every possible single stuck-at fault in the circuit. This dissertation describes a new method for generating test patterns: the Boolean satisfiability method. The new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the addition of any heuristic used by the structural search methods. The Boolean satisfiability method has produced excellent results on popular test pattern generation benchmarks.

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