Algorithms for technology mapping based on binary decision diagrams and on Boolean operations

Algorithms and a computer-aided design tool, called Ceres, for technology mapping of both completely specified and incompletely specified logic networks are introduced. The algorithms are based on Boolean techniques for matching, i.e., for the recognition of the equivalence between a portion of a network and library cells. A novel matching algorithm, using ordered binary decision diagrams, is described. It exploits the notion of symmetry to achieve higher computational efficiency. A matching technique that takes advantage of don't-care conditions by means of a compatibility graph is also described. A strategy for timing-driven technology mapping, based on iterative improvement, is presented. Experimental results indicate that these techniques generate good-quality solutions and require short run times and limited memory space. >

[1]  Saburo Muroga,et al.  Threshold logic and its applications , 1971 .

[2]  Frederic Mailhot,et al.  Technology Mapping for VLSI Circuits Exploiting Boolean Properties and Operations , 1994 .

[3]  D. Gregory,et al.  SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic , 1986, 23rd ACM/IEEE Design Automation Conference.

[4]  Robert K. Brayton,et al.  Extracting local don't cares for network optimization , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[5]  Giovanni De Micheli,et al.  The Olympus synthesis system , 1990, IEEE Design & Test of Computers.

[6]  Chih-Jen Lin,et al.  Enhanced controllability for IDDQ test sets using partial scan , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  G. De Micheli,et al.  Logic transformations for synchronous logic synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[8]  C. L. Liu.  Elements of Discrete Mathematics , 1985 .

[9]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .

[10]  R. Keith Treece,et al.  Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets , 1990, Proceedings. International Test Conference 1990.

[11]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[13]  M. C. Lega.  Mapping properties of multi-level logic synthesis operations , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[14]  Edward J. McCluskey,et al.  Detection of group invariance or total symmetry of a Boolean function , 1956 .

[15]  Robert K. Brayton,et al.  Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[16]  Saburo Muroga,et al.  SYLON-DREAM: a multi-level network synthesizer , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[17]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[18]  P. G. Paulin,et al.  Logic decomposition algorithms for the timing optimization of multi-level logic , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[19]  Jochen A. G. Jess,et al.  Technology mapping for standard-cell generators , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[20]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[21]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[23]  Giovanni De Micheli,et al.  Observability don't care sets and Boolean relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[24]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[25]  Robert K. Brayton,et al.  The use of observability and external don't cares for the simplification of multi-level networks , 1991, DAC '90.

[26]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[27]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[28]  Robert K. Brayton,et al.  Consistency and observability invariance in multi-level logic synthesis , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[29]  Giovanni De Micheli,et al.  Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits , 1987, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Gary D. Hachtel,et al.  BOLD: The Boulder Optimal Logic Design system , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

[31]  F. Brglez,et al.  McMAP: a fast technology mapping procedure for multi-level logic synthesis , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.