A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface
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Byungsub Kim | Jae-Yoon Sim | Hong-June Park | Young Jae Jang | Kyunghoon Kim | Ji-Hoon Lim | Hae-Kang Jung | Soo-Min Lee | Il-Min Yi | Dae-Han Kwon
[1] 이재승,et al. A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration , 2008 .
[2] Ting Wu,et al. A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface , 2012, IEEE Journal of Solid-State Circuits.
[3] Jae-Yoon Sim,et al. A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface , 2011, IEEE Journal of Solid-State Circuits.
[4] Won Namgoong,et al. High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding , 2009, IEEE Journal of Solid-State Circuits.
[5] Byungsub Kim,et al. A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.
[6] Anthony Chan Carusone,et al. Differential signaling with a reduced number of signal paths , 2001 .
[7] J. L. Zerbe. A 2Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receviers , 2001 .
[8] Yue Lu,et al. A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques , 2011, IEEE Journal of Solid-State Circuits.
[9] 심재윤,et al. A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface , 2008 .
[10] Won Namgoong,et al. Multilevel differential encoding with precentering for high-speed parallel link transceiver , 2005, IEEE Journal of Solid-State Circuits.
[11] Jae-Yoon Sim,et al. A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[12] 심재윤,et al. EMI issues in pseudo-differential signaling for SDRAM interface , 2015 .
[13] Young-Hyun Jun,et al. A 0.13-$\mu$ m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN , 2009, IEEE Journal of Solid-State Circuits.
[14] Byungsub Kim,et al. A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.
[15] Changsik Yoo,et al. Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface , 2010 .
[16] Karthik Gopalakrishnan,et al. Single-ended transceiver design techniques for 5.33Gb/s graphics applications , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[17] Amin Shokrollahi,et al. 26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[18] Woo-Jin Lee,et al. An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion , 2008, IEEE Journal of Solid-State Circuits.