论文信息 - Simulation and implementation of an analog VLSI pulse-coupled neural network for image segmentation

Simulation and implementation of an analog VLSI pulse-coupled neural network for image segmentation

We present a massively parallel VLSI realization of a pulse-coupled neural network for image segmentation. The network comprises 128 /spl times/ 128 simple nonleaky integrate-and-fire (IAF) neurons with self-organizing inter-neural connections. The prototype implementation also contains analog memories for image storing and a digital readout circuit using an address-event-representation (AER) protocol. The chip has been designed in an Infineon 0.13 /spl mu/m standard CMOS technology.

[1] Eugene M. Izhikevich,et al. Weakly pulse-coupled oscillators, FM interactions, synchronization, and oscillatory associative memory , 1999, IEEE Trans. Neural Networks.

[2] Christoph von der Malsburg,et al. The Correlation Theory of Brain Function , 1994 .

[3] D. Hubel,et al. Receptive fields, binocular interaction and functional architecture in the cat's visual cortex , 1962, The Journal of physiology.

[4] Giacomo Indiveri,et al. Modeling Selective Attention Using a Neuromorphic Analog VLSI Device , 2000, Neural Computation.

[5] Carver Mead,et al. Analog VLSI and neural systems , 1989 .

[6] Russell Beale,et al. Handbook of Neural Computation , 1996 .

[7] Ulrich Ramacher,et al. Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity , 2002, Proceedings of the 12th IEEE Workshop on Neural Networks for Signal Processing.

[8] Vittorio Dante,et al. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory , 2003, IEEE Trans. Neural Networks.