Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS

This paper describes using theory, computer simulations, and laboratory measurements a new class of real-time reconfigurable UV-programmable floating-gate (FGUVMOS) linear threshold elements operating with current levels typically in the pA to /spl mu/A range, in standard double-poly 0.6 /spl mu/m CMOS, providing an ultra low-power potential. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I-O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components compared to previously reported FGUVMOS. 2-MOSFET circuits able to implement CARRY, NOR, NAND, and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. The basic linear threshold element proposed is considered as a potential basic building block in neural networks.

[1]  K. Yang,et al.  Subthreshold analysis of floating-gate MOSFET's , 1993, [1993] Proceedings of the Tenth Biennial University/Government/Industry Microelectronics Symposium.

[2]  T. Saether,et al.  Floating-gate low-voltage/low-power linear threshold element for neural computation , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[3]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[4]  Snorre Aunet Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS , 2002 .

[5]  Trond Ytterdal,et al.  Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[6]  Valeriu Beiu,et al.  On limited fan-in optimal neural networks , 1997, Proceedings 4th Brazilian Symposium on Neural Networks.

[7]  Vasken Zaven Bohossian,et al.  Neural logic: theory and implementation , 1998 .

[8]  M. Aberg,et al.  Improved neuron MOS-transistor structures for integrated neural network circuits , 2001 .

[9]  Gloria Huertas,et al.  A practical floating-gate Muller-C element using vMOS threshold gates , 2001 .

[10]  Saburo Muroga,et al.  Threshold logic and its applications , 1971 .

[11]  J. Ramirez-Angulo,et al.  Modeling multiple-input floating-gate transistors for analog signal processing , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[12]  Jehoshua Bruck,et al.  Neural computation of arithmetic functions , 1990 .

[13]  Paul Hasler,et al.  Cadence-based simulation of floating-gate circuits using the EKV model , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[14]  Andreas G. Andreou,et al.  Current-mode subthreshold MOS circuits for analog VLSI neural systems , 1991, IEEE Trans. Neural Networks.

[15]  Yngvar Berg,et al.  Area efficient circuit tuning with floating-gate techniques , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[16]  Snorre Aunet,et al.  Four-MOSFET Floating-Gate UV-Programmable Elements for Multifunction Binary Logic , 2001 .

[17]  Valeriu Beiu,et al.  Deeper Sparsely Nets can be Optimal , 1998, Neural Processing Letters.

[18]  Trond Ytterdal,et al.  A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[19]  Tor Sverre Lande,et al.  FLOGIC-Floating-gate logic for low-power operation , 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

[20]  Yngvar Berg,et al.  Ultra low-voltage/low-power digital floating-gate circuits , 1999 .

[21]  Carver A. Mead,et al.  Neuromorphic electronic systems , 1990, Proc. IEEE.

[22]  Tor Sverre Lande,et al.  Overview of floating-gate devices, circuits, and systems , 2001 .

[23]  Miguel Figueroa,et al.  Adaptive CMOS: from biological inspiration to systems-on-a-chip , 2002, Proc. IEEE.