A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded because of increased process variation and decreased read current. In this brief, we propose an offset-canceling dual-stage sensing circuit (OCDS-SC) that has the two major advantages of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a read access yield of 99.93% for 32 Mb (6.6 sigma) with a read current of 15 μA and sensing time of 3.4 ns.

[1]  Yiran Chen,et al.  A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme , 2012, IEEE Journal of Solid-State Circuits.

[2]  Hanwool Jeong,et al.  Comparative Study of Various Latch-Type Sense Amplifiers , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Meng-Fan Chang,et al.  An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory , 2013, IEEE Journal of Solid-State Circuits.

[4]  Chih-Kong Ken Yang,et al.  A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs) , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[5]  Seung H. Kang,et al.  A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[6]  K. Ono,et al.  A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[7]  Doris Schmitt-Landsiedel,et al.  Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  Seong-Ook Jung,et al.  A Split-Path Sensing Circuit for Spin Torque Transfer MRAM , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Meng-Fan Chang,et al.  19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[10]  Seong-Ook Jung,et al.  Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Chih-Kong Ken Yang,et al.  Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Seong-Ook Jung,et al.  An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Yukio Hayakawa,et al.  An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput , 2012, IEEE Journal of Solid-State Circuits.

[14]  Luan Tran,et al.  45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[15]  Seong-Ook Jung,et al.  A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Seong-Ook Jung,et al.  An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Seong-Ook Jung,et al.  Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Seong-Ook Jung,et al.  Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Meng-Fan Chang,et al.  A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time , 2012, 2012 IEEE International Solid-State Circuits Conference.