Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study

The number and diversity of consumer devices are growing rapidly, alongside their target applications' memory consumption. Unfortunately, DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. Since entirely replacing DRAM with NVM in consumer devices imposes large system integration and design challenges, recent works propose extending the total main memory space available to applications by using NVM as swap space for DRAM. However, no prior work analyzes the implications of enabling a real NVM-based swap space in real consumer devices. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We extensively examine system performance and energy consumption when the NVM device is used as swap space for DRAM main memory to effectively extend the main memory capacity. For our analyses, we equip real web-based Chromebook computers with the Intel Optane SSD, which is a state-of-the-art low-latency NVM-based SSD device. We compare the performance and energy consumption of interactive workloads running on our Chromebook with NVM-based swap space, where the Intel Optane SSD capacity is used as swap space to extend main memory capacity, against two state-of-the-art systems: (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-the-art (yet slower) off-the-shelf NAND-flash-based SSD, which we use as a swap space of equivalent size as the NVM-based swap space.

[1]  Ambalegin Ambalegin,et al.  Address Term Used By The Instagram Users , 2022, Humanitatis : Journal of Language and Literature.

[2]  Haikun Liu,et al.  Towards low-latency I/O services for mixed workloads using ultra-low latency SSDs , 2022, ICS.

[3]  Jeremie S. Kim,et al.  Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices , 2022, 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

[4]  O. Mutlu,et al.  Sibyl: adaptive and extensible data placement in hybrid storage systems using online reinforcement learning , 2022, ISCA.

[5]  Lingfang Zeng,et al.  A Multi-hashing Index for hybrid DRAM-NVM memory systems , 2022, J. Syst. Archit..

[6]  J. Rao,et al.  Characterizing the performance of intel optane persistent memory: a close look at its on-DIMM buffering , 2022, EuroSys.

[7]  M. Erez,et al.  HeMem: Scalable Tiered Memory Management for Big Data Applications and Real NVM , 2021, SOSP.

[8]  Onur Mutlu,et al.  Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications , 2021, MICRO.

[9]  Jeremie S. Kim,et al.  A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses , 2021, MICRO.

[10]  Qiang Cao,et al.  A Case Study of Migrating RocksDB on Intel Optane Persistent Memory , 2021, 2021 IEEE International Conference on Networking, Architecture and Storage (NAS).

[11]  Pankaj Mehra,et al.  Twizzler: A Data-centric OS for Non-volatile Memory , 2021, USENIX Annual Technical Conference.

[12]  Amirali Boroumand Practical Mechanisms for Reducing Processor-Memory Data Movement in Modern Workloads , 2021 .

[13]  Song Jiang,et al.  ChameleonDB: a key-value store for optane persistent memory , 2021, EuroSys.

[14]  Nagarajan Kandasamy,et al.  Aging-Aware Request Scheduling for Non-Volatile Main Memory , 2020, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

[15]  Yusen Li,et al.  An NVM SSD-Optimized Query Processing Framework , 2020, CIKM.

[16]  Ran Ginosar,et al.  WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders , 2020, 2020 IEEE 38th International Conference on Computer Design (ICCD).

[17]  Feng Chen,et al.  From Flash to 3D XPoint: Performance Bottlenecks and Potentials in RocksDB with Storage Evolution , 2020, 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[18]  Tei-Wei Kuo,et al.  Acclaim: Adaptive Memory Reclaim to Improve User Experience in Android Systems , 2020, USENIX Annual Technical Conference.

[19]  Samuel Madden,et al.  Large-scale in-memory analytics on Intel® Optane™ DC persistent memory , 2020, DaMoN.

[20]  Jaeyoung Do,et al.  Lessons learned from the early performance evaluation of Intel optane DC persistent memory in DBMS , 2020, DaMoN.

[21]  Nagarajan Kandasamy,et al.  Improving phase change memory performance with data content aware access , 2020, ISMM.

[22]  Sangsu Park,et al.  Conductive-bridging random-access memories for emerging neuromorphic computing. , 2020, Nanoscale.

[23]  Mario Badr,et al.  Mocktails: Capturing the Memory Behaviour of Proprietary Mobile Architectures , 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

[24]  Onur Mutlu,et al.  Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques , 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

[25]  Jinkyu Jeong,et al.  A Case for Hardware-Based Demand Paging , 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

[26]  Cristiano Giuffrida,et al.  TRRespass: Exploiting the Many Sides of Target Row Refresh , 2020, 2020 IEEE Symposium on Security and Privacy (SP).

[27]  D. Taussky,et al.  Twitter , 2020, American journal of clinical oncology.

[28]  David J. Lilja,et al.  Exploring Performance Characteristics of the Optane 3D Xpoint Storage Technology , 2020, ACM Trans. Model. Perform. Evaluation Comput. Syst..

[29]  Young Ik Eom,et al.  H-BFQ: Supporting Multi-Level Hierarchical Cgroup in BFQ Scheduler , 2020, 2020 IEEE International Conference on Big Data and Smart Computing (BigComp).

[30]  Yu Hua,et al.  A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Adrian Jackson,et al.  An early evaluation of Intel's optane DC persistent memory module and its impact on high-performance scientific applications , 2019, SC.

[32]  Evgeny Epifanovsky,et al.  Performance Evaluation of the Intel Optane DC Memory With Scientific Benchmarks , 2019, 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC).

[33]  Frank Mueller,et al.  Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules , 2019, MEMSYS.

[34]  Jongseok Kim,et al.  $ezswap$ : Enhanced Compressed Swap Scheme for Mobile Devices , 2019, IEEE Access.

[35]  Hyokyung Bahn,et al.  Analysis of Smartphone I/O Characteristics — Toward Efficient Swap in a Smartphone , 2019, IEEE Access.

[36]  Nagarajan Kandasamy,et al.  Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories , 2019, ACM Trans. Embed. Comput. Syst..

[37]  Ivy B. Peng,et al.  System evaluation of the Intel optane byte-addressable NVM , 2019, MEMSYS.

[38]  Steven Swanson,et al.  An Empirical Guide to the Behavior and Use of Scalable Persistent Memory , 2019, FAST.

[39]  Andrea C. Arpaci-Dusseau,et al.  Exploiting Intel Optane SSD for Microsoft SQL Server , 2019, DaMoN.

[40]  Ismail Oukid,et al.  Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations , 2019, DaMoN.

[41]  Onur Mutlu,et al.  Panthera: holistic memory management for big data processing over hybrid memories , 2019, PLDI.

[42]  Heeket Mehta,et al.  Google Maps , 2019, International Journal of Computer Applications.

[43]  Onur Mutlu,et al.  RowHammer: A Retrospective , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[44]  Keshav Pingali,et al.  Single machine graph analytics on massive datasets using Intel optane DC persistent memory , 2019, Proc. VLDB Endow..

[45]  Onur Mutlu,et al.  An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories , 2019, IEEE Transactions on Computers.

[46]  Xiao Liu,et al.  Basic Performance Measurements of the Intel Optane DC Persistent Memory Module , 2019, ArXiv.

[47]  Hyokyung Bahn,et al.  Comparison of Hybrid and Hierarchical Swap Architectures in Android by using NVM , 2018, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE.

[48]  Gang Wang,et al.  Performance Analysis of 3D XPoint SSDs in Virtualized and Non-Virtualized Environments , 2018, 2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS).

[49]  Chia-Lin Yang,et al.  LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling , 2018, ArXiv.

[50]  Mahmut T. Kandemir,et al.  FlashShare: Punching Through Server Storage Stack from Kernel to Firmware for Ultra-Low Latency SSDs , 2018, OSDI.

[51]  Sai Narasimhamurthy,et al.  Characterizing Deep-Learning I/O Workloads in TensorFlow , 2018, 2018 IEEE/ACM 3rd International Workshop on Parallel Data Storage & Data Intensive Scalable Computing Systems (PDSW-DISCS).

[52]  Eiji Yoshida,et al.  Reducing CPU Power Consumption for Low-Latency SSDs , 2018, 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

[53]  Onur Mutlu,et al.  What Your DRAM Power Models Are Not Telling You , 2018, Proc. ACM Meas. Anal. Comput. Syst..

[54]  Onur Mutlu,et al.  Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation , 2018, SIGMETRICS.

[55]  Onur Mutlu,et al.  FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives , 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

[56]  Joon-Sung Yang,et al.  Optimized I/O Determinism for Emerging NVM-based NVMe SSD in an Enterprise System , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[57]  Joo Young Hwang,et al.  2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives , 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

[58]  Rachata Ausavarungnirun,et al.  Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks , 2018, ASPLOS.

[59]  Onur Mutlu,et al.  MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices , 2018, FAST.

[60]  Onur Mutlu,et al.  HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness , 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[61]  Kevin K. Chang,et al.  Understanding and Improving the Latency of DRAM-Based Memory Systems , 2017, ArXiv.

[62]  Gang Cao,et al.  SPDK: A Development Kit to Build High Performance Storage Applications , 2017, 2017 IEEE International Conference on Cloud Computing Technology and Science (CloudCom).

[63]  Yang Li,et al.  Building NVRAM-Aware Swapping Through Code Migration in Mobile Devices , 2017, IEEE Transactions on Parallel and Distributed Systems.

[64]  Yang Li,et al.  Non-Volatile Memory Based Page Swapping for Building High-Performance Mobile Devices , 2017, IEEE Transactions on Computers.

[65]  Thomas E. Anderson,et al.  Strata: A Cross Media File System , 2017, SOSP.

[66]  Onur Mutlu,et al.  Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content , 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[67]  Gi-Ho Park,et al.  NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors , 2017, IEEE Transactions on Parallel and Distributed Systems.

[68]  Jin-Soo Kim,et al.  Application-Aware Swapping for Mobile Systems , 2017, ACM Trans. Embed. Comput. Syst..

[69]  Jin Sun,et al.  Utility-Based Hybrid Memory Management , 2017, 2017 IEEE International Conference on Cluster Computing (CLUSTER).

[70]  Yiran Chen,et al.  GraphR: Accelerating Graph Processing Using ReRAM , 2017, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[71]  Dan Williams,et al.  Platform Storage Performance With 3D XPoint Technology , 2017, Proceedings of the IEEE.

[72]  Dong Li,et al.  Early Evaluation of Intel Optane Non-Volatile Memory with HPC I/O Workloads , 2017, ArXiv.

[73]  Onur Mutlu,et al.  Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives , 2017, Proceedings of the IEEE.

[74]  Onur Mutlu,et al.  The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[75]  Tao Li,et al.  SmartSwap: High-performance and user experience friendly swapping in mobile systems , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[76]  Rachata Ausavarungnirun,et al.  Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms , 2017, SIGMETRICS.

[77]  O. Mutlu,et al.  Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms , 2017, SIGMETRICS.

[78]  Thomas P. Parnell,et al.  Temporal correlation detection using computational phase-change memory , 2017, Nature Communications.

[79]  SukHwan Lim,et al.  Driving Innovation in Memory Architecture of Consumer Hardware with Digital Photography and Machine Intelligence Use Cases , 2017, 2017 IEEE International Memory Workshop (IMW).

[80]  H.-S. Philip Wong,et al.  Face classification using electronic synapses , 2017, Nature Communications.

[81]  Onur Mutlu,et al.  The RowHammer problem and other issues we may face as memory becomes denser , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[82]  Jin-Soo Kim,et al.  A user-space storage I/O framework for NVMe SSDs in mobile smart devices , 2017, IEEE Transactions on Consumer Electronics.

[83]  Yiran Chen,et al.  PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[84]  Onur Mutlu,et al.  Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[85]  Ada Gavrilovska,et al.  Energy aware persistence: Reducing energy overheads of memory-based persistence in NVMs , 2016, 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT).

[86]  O. Mutlu,et al.  Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory , 2016, IEEE Journal on Selected Areas in Communications.

[87]  Tei-Wei Kuo,et al.  Improving PCM Endurance with a Constant-Cost Wear Leveling Design , 2016, ACM Trans. Design Autom. Electr. Syst..

[88]  Jin-Soo Kim,et al.  NVMeDirect: A User-space I/O Framework for Application-specific Optimization on NVMe SSDs , 2016, HotStorage.

[89]  Yu Wang,et al.  PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[90]  Onur Mutlu,et al.  Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization , 2016, SIGMETRICS.

[91]  Catherine Graves,et al.  Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[92]  Kartik Mohanram,et al.  SECRET: Smartly EnCRypted Energy efficienT non-volatile memories , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[93]  Onur Mutlu,et al.  PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM , 2016, 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

[94]  Vijay Janapa Reddi,et al.  Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[95]  Weimin Zheng,et al.  MARS: Mobile Application Relaunching Speed-Up through Flash-Aware Page Swapping , 2016, IEEE Trans. Computers.

[96]  Wei-Kuan Shih,et al.  Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[97]  Tajana Simunic,et al.  CAUSE: Critical application usage-aware memory system using non-volatile memory for mobile devices , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[98]  Dimitrios S. Nikolopoulos,et al.  Energy-Efficient Hybrid DRAM/NVM Main Memory , 2015, 2015 International Conference on Parallel Architecture and Compilation (PACT).

[99]  Sang-Won Lee,et al.  SQLite Optimization with Phase Change Memory for Mobile Applications , 2015, Proc. VLDB Endow..

[100]  Qiang Wu,et al.  Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field , 2015, 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[101]  Onur Mutlu,et al.  AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems , 2015, 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[102]  Onur Mutlu,et al.  Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery , 2015, 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[103]  Eric Shiu,et al.  System challenges and hardware requirements for future consumer devices: From wearable to ChromeBooks and devices in-between , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[104]  Gu-Yeon Wei,et al.  Profiling a warehouse-scale computer , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[105]  Jun Yang,et al.  Exploit imbalanced cell writes to mitigate write disturbance in dense Phase Change Memory , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[106]  Rajat Mahapatra,et al.  Conductive-bridging random access memory: challenges and opportunity for 3D architecture , 2015, Nanoscale Research Letters.

[107]  Gennady Pekhimenko,et al.  Adaptive-latency DRAM: Optimizing DRAM timing for the common-case , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[108]  Rasit O. Topaloglu,et al.  More than Moore Technologies for Next Generation Computer Design , 2015 .

[109]  Onur Mutlu,et al.  Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories , 2014, ACM Trans. Archit. Code Optim..

[110]  Chris Fallin,et al.  Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[111]  Onur Mutlu,et al.  Research Problems and Opportunities in Memory Systems , 2014, Supercomput. Front. Innov..

[112]  Edwin Hsing-Mean Sha,et al.  Building high-performance smartphones via non-volatile memory: The swap approach , 2014, 2014 International Conference on Embedded Software (EMSOFT).

[113]  Timothy Roscoe,et al.  Arrakis , 2014, OSDI.

[114]  Qingfeng Zhuge,et al.  Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[115]  Edwin Hsing-Mean Sha,et al.  DR. Swap: Energy-efficient paging for smartphones , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[116]  Yuan Xue,et al.  Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[117]  Jiwu Shu,et al.  WL-Reviver: A Framework for Reviving any Wear-Leveling Techniques in the Face of Failures on Phase Change Memory , 2014, 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[118]  Hyeonsang Eom,et al.  OS I/O Path Optimizations for Flash Solid-state Drives , 2014, USENIX Annual Technical Conference.

[119]  Onur Mutlu,et al.  Improving DRAM performance by parallelizing refreshes with accesses , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[120]  Onur Mutlu,et al.  The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study , 2014, SIGMETRICS '14.

[121]  A. Belcaster Minecraft , 2014 .

[122]  Dongkun Shin,et al.  Differentiated space allocation for wear leveling on phase-change memory-based storage device , 2014, IEEE Transactions on Consumer Electronics.

[123]  Lixin Zhang,et al.  Moby: A mobile benchmark suite for architectural simulators , 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[124]  Steven Swanson,et al.  DC express: shortest latency protocol for reading phase change memory over PCI express , 2014, FAST.

[125]  Onur Mutlu,et al.  Linearly compressed pages: A low-complexity, low-latency main memory compression framework , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[126]  Tavish Armstrong,et al.  The Performance of Open Source Applications , 2013 .

[127]  Rami G. Melhem,et al.  Writeback-aware bandwidth partitioning for multi-core systems with PCM , 2013, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques.

[128]  Carole-Jean Wu,et al.  Performance, energy characterizations and architectural implications of an emerging mobile platform benchmark suite - MobileBench , 2013, 2013 IEEE International Symposium on Workload Characterization (IISWC).

[129]  Philippe Bonnet,et al.  Linux block IO: introducing multi-queue SSD access on multi-core systems , 2013, SYSTOR '13.

[130]  Rami G. Melhem,et al.  Bit mapping for balanced PCM cell programming , 2013, ISCA.

[131]  Onur Mutlu,et al.  An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms , 2013, ISCA.

[132]  Onur Mutlu,et al.  Memory scaling: A systems architecture perspective , 2013, 2013 5th IEEE International Memory Workshop.

[133]  Jun Yang,et al.  Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory , 2013, TACO.

[134]  Mahmut T. Kandemir,et al.  Evaluating STT-RAM as an energy-efficient main memory alternative , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[135]  Yifeng Zhu,et al.  Accelerating write by exploiting PCM asymmetries , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[136]  Kang L. Wang,et al.  Low-power non-volatile spintronic memory: STT-RAM and beyond , 2013 .

[137]  Jun Yang,et al.  FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[138]  Rachata Ausavarungnirun,et al.  Row buffer locality aware caching policies for hybrid memories , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[139]  Jing Li,et al.  A case for small row buffers in non-volatile main memories , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[140]  Onur Mutlu,et al.  Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management , 2012, IEEE Computer Architecture Letters.

[141]  Richard Veras,et al.  RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[142]  Tei-Wei Kuo,et al.  Age-based PCM wear leveling with nearly zero search cost , 2012, DAC Design Automation Conference 2012.

[143]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.

[144]  Steven Swanson,et al.  Providing safe, user space access to fast, solid state disks , 2012, ASPLOS XVII.

[145]  Frank Hady,et al.  When poll is better than interrupt , 2012, FAST.

[146]  Moinuddin K. Qureshi Pay-As-You-Go: Low-overhead hard-error correction for phase change memories , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[147]  Ronald G. Dreslinski,et al.  Full-system analysis and characterization of interactive smartphone applications , 2011, 2011 IEEE International Symposium on Workload Characterization (IISWC).

[148]  H. Howie Huang,et al.  Energy-aware writes to non-volatile main memory , 2011, OPSR.

[149]  Chris Fallin,et al.  Memory power management via dynamic voltage/frequency scaling , 2011, ICAC '11.

[150]  Rami G. Melhem,et al.  Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory , 2011, (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.

[151]  Qingyuan Deng,et al.  MemScale: active low-power modes for main memory , 2011, ASPLOS XVI.

[152]  Luis A. Lastras,et al.  Practical and secure PCM systems by online detection of malicious write streams , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[153]  Sungjoo Hong,et al.  Memory technology trend and future challenges , 2010, 2010 International Electron Devices Meeting.

[154]  Hisashi Shima,et al.  Resistive Random Access Memory (ReRAM) Based on Metal Oxides , 2010, Proceedings of the IEEE.

[155]  Onur Mutlu,et al.  Phase change memory architecture and the quest for scalability , 2010, Commun. ACM.

[156]  Moinuddin K. Qureshi,et al.  Morphable memory system: a robust architecture for exploiting multi-level phase change memories , 2010, ISCA.

[157]  Mircea R. Stan,et al.  Advances and Future Prospects of Spin-Transfer Torque Random Access Memory , 2010, IEEE Transactions on Magnetics.

[158]  Chakravarthy Gopalan,et al.  Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process , 2010, 2010 IEEE International Memory Workshop.

[159]  Moinuddin K. Qureshi,et al.  Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[160]  Rami G. Melhem,et al.  Increasing PCM main memory lifetime , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[161]  Naehyuck Chang,et al.  Energy- and endurance-aware design of phase change memory caches , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[162]  Vijayalakshmi Srinivasan,et al.  Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[163]  Alex Wright,et al.  Ready for a Web OS? , 2009, Commun. ACM.

[164]  Arijit Raychowdhury,et al.  Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[165]  Tajana Simunic,et al.  PDRAM: A hybrid PRAM and DRAM main memory system , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[166]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[167]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[168]  Jun Yang,et al.  A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.

[169]  Charles Reis,et al.  Isolating web programs in modern browser architectures , 2009, EuroSys '09.

[170]  Kailash Gopalakrishnan,et al.  Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..

[171]  M. Breitwisch Phase Change Memory , 2008, 2008 International Interconnect Technology Conference.

[172]  Z. Diao,et al.  Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory , 2007 .

[173]  J. Scott,et al.  Applications of Modern Ferroelectrics , 2007, Science.

[174]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[175]  R. Symanczyk,et al.  Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[176]  Brian K. Tanaka Monitoring virtual memory with vmstat , 2005 .

[177]  Marco Cesati,et al.  Understanding the Linux Kernel - from I / O ports to process management: covers Linux Kernel version 2.4 (2. ed.) , 2005 .

[178]  Robert H. Dennard,et al.  Challenges and future directions for the scaling of dynamic random-access memory (DRAM) , 2002, IBM J. Res. Dev..

[179]  Matthew R. Guthaus,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538).

[180]  Walter Hartner,et al.  FeRAM technology for high density applications , 2001, Microelectron. Reliab..

[181]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[182]  J. Scott,et al.  Ferroelectric memories , 1997, Science.

[183]  Hui Zhang,et al.  Hierarchical packet fair queueing algorithms , 1996, SIGCOMM '96.

[184]  David Bondurant,et al.  Ferroelectronic ram memory family for critical data storage , 1990 .

[185]  T. Rabl,et al.  PerMA-Bench: Benchmarking Persistent Memory Access , 2022, Proc. VLDB Endow..

[186]  Andrea C. Arpaci-Dusseau,et al.  The Storage Hierarchy is Not a Hierarchy: Optimizing Caching on Modern Storage Devices with Orthus , 2021, FAST.

[187]  冯利芳 Facebook , 2020, The SAGE International Encyclopedia of Mass Media and Society.

[188]  Hyokyung Bahn,et al.  Maintaining Application Context of Smartphones by Selectively Supporting Swap and Kill , 2020, IEEE Access.

[189]  Steve Scargall,et al.  Introducing the Persistent Memory Development Kit , 2020 .

[190]  Henry M. Levy,et al.  End the Senseless Killing: Improving Memory Management for Mobile Operating Systems , 2020, USENIX Annual Technical Conference.

[191]  Jin Xiong,et al.  SplitKV: Splitting IO Paths for Different Sized Key-Value Items with Advanced Storage Devices , 2020, HotStorage.

[192]  Manolis Marazakis,et al.  Optimizing Memory-mapped I/O for Fast Storage Devices , 2020, USENIX Annual Technical Conference.

[193]  Bryan Harris,et al.  Ultra-Low Latency SSDs' Impact on Overall Energy Efficiency , 2020, HotStorage.

[194]  Andrea C. Arpaci-Dusseau,et al.  Towards an Unwritten Contract of Intel Optane SSD , 2019, HotStorage.

[195]  Mambo G. Mupepi WhatsApp Messenger , 2019, Global Cyber Security Labor Shortage and International Business Risk.

[196]  Jawed Karim YouTube , 2019, Social Media.

[197]  Jinkyu Jeong,et al.  Asynchronous I/O Stack: A Low-latency Kernel I/O Stack for Ultra-Low Latency SSDs , 2019, USENIX Annual Technical Conference.

[198]  G. Atwood PCM Applications and an Outlook to the Future , 2018 .

[199]  Vijay Janapa Reddi,et al.  Two Billion Devices and Counting , 2018, IEEE Micro.

[200]  Vijay Janapa Reddi,et al.  Storage on Your SmartPhone Uses More Energy Than You Think , 2017, HotStorage.

[201]  Onur Mutlu,et al.  NVMOVE: Helping Programmers Move to Byte-Based Persistence , 2016, INFLOW@OSDI.

[202]  Xiaowei Li,et al.  Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[203]  Onur Mutlu,et al.  Main Memory Scaling: Challenges and Solution Directions , 2015 .

[204]  Hongzhong Zheng,et al.  Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling , 2014 .

[205]  Onur Mutlu,et al.  Memory Systems , 2014, Computing Handbook, 3rd ed..

[206]  Onur Mutlu,et al.  Techniques for Data Mapping and Buffering to Exploit Asymmetry in Multi-Level Cell (Phase Change) Memory , 2013 .

[207]  Onur Mutlu,et al.  A Case for Effic ient Hardware/Soft ware Cooperative Management of Storage and Memory , 2013 .

[208]  J Joshua Yang,et al.  Memristive devices for computing. , 2013, Nature nanotechnology.

[209]  Rami G. Melhem,et al.  Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems , 2012, TACO.

[210]  Charlie Collins,et al.  ANDROID IN PRACTICE , 2011 .

[211]  Arnaldo Carvalho de Melo,et al.  The New Linux ’ perf ’ Tools , 2010 .

[212]  It Informatika,et al.  Adobe Acrobat Reader , 2010 .

[213]  Jun Yang,et al.  Phase-Change Technology and the Future of Main Memory , 2010, IEEE Micro.

[214]  Adam Barth,et al.  The Security Architecture of the Chromium Browser , 2009 .

[215]  Andrew S. Tanenbaum,et al.  Operating systems: design and implementation , 1987, Prentice-Hall software series.