Fault tolerance infrastructure and its reuse for offline testing: synergies of a unified architecture to cope with soft errors and hard faults

The evolution of digital circuits from a few application areas to omnipresence in everyday life has been enabled by the ability to dramatically increase integration density through scaling. However, the continuation of scaling gets more difficult with every generation and poses severe challenges on reliability. Throughout the manufacturing process the appearance of defects cannot be avoided and further deteriorates with scaling. Hence, the reliability at timepoint zero denoted by the manufacturing yield is not ideal and some defective chips will produce wrong output signals. For this reason, the presence of such hard faults needs to be shown prior to delivery during test where automatic test equipment (ATE) is used to apply a test set that covers a predefined set of modeled defects. As some potential defect locations are hard to test using the chips operational interface, additional dedicated test infrastructure is included on chip that provides test access. Throughout the operational lifetime reliability is threatened by soft errors that originate from interactions of radiation with semiconductor devices and potentially manifest in sequential state corruptions. With further raising soft error rates aggravated by scaling high reliability is maintained by the inclusion of fault tolerance infrastructure able to detect, localize and ideally correct soft errors. Thus, the orthogonal combination of two independent infrastructures elevates the area overhead although test support and fault tolerance are never required concurrently. This work proposes a unified architecture that employs a common infrastructure to provide fault tolerance during operation and test access during test. Similarities between both fields are successfully exploited and traced back to the combination of an efficient sequential state checksum with an effective state update by bit-flipping. Experiments on public and industrial circuits evaluate the unified architecture in both fields and show an improved area efficiency as well as successful correction during fault tolerance. During test, the results substantiate advantages with respect to test time, test volume, peak and average test power as well as test energy. Die Fahigkeit die Integrationsdichte mittels Skalierung drastisch zu steigern, hat die Evolution digitaler Schaltungen von ein paar Anwendungsgebieten zur Allgegenwart im taglichen Leben ermoglicht. Eine Fortfuhrung der Skalierung gestaltet sich jedoch von Generation zu Generation schwieriger und stellt daruber hinaus ernste Herausforderungen an die Zuverlassigkeit. Das Auftreten von Defekten kann wahrend des Herstellungsprozesses nicht verhindert werden und verschlimmert sich unter Skalierung weiter. Die Zuverlassigkeit zum Zeitpunkt null, ausgedruckt durch die Produktionsausbeute, ist somit nicht ideal und einige defekte Chips erzeugen falsche Ausgangssignale. Aus diesem Grund ist es notwendig vorhandene permanente Fehler (hard faults) vor der Auslieferung mittels Test zu erkennen. Dabei wird eine vorbestimmte Menge von Defekten in einer Testmenge modelliert und diese durch Testautomaten (Automatic Test Equipment, ATE) auf jeden Chip angewendet. Da einige der potentiellen Defektstellen mittels der funktionalen Chipschnittstellen nur schwer zu testen sind, wird dem Chip zusatzlich dedizierte Testinfrastruktur hinzugefugt, die einen Testzugriff bietet. Wahrend des Systembetriebs wird die Zuverlassigkeit durch transiente Fehler (soft errors) bedroht, die durch die Interaktion von Strahlung mit den Halbleitermaterialien hervorgerufen werden. Diese manifestieren sich moglicherweise in Veranderungen des sequentiellen Schaltungszustands. Mit weiter steigenden transienten Fehlerraten, die durch Skalierung verstarkt werden, wird eine hohe Zuverlassigkeit durch das Hinzufugen von Fehlertoleranzinfrastruktur beibehalten, die transiente Fehler erkennen, lokalisieren und idealerweise korrigieren kann. Folglich erhoht die orthogonale Kombination zweier unabhangiger Infrastrukturen den Flachenbedarf, obwohl Testunterstutzung und Fehlertoleranz nie gleichzeitig benotigt werden. Diese Arbeit stellt eine vereinheitlichte Architektur vor, die eine gemeinsame Infrastruktur verwendet, um Fehlertoleranz wahrend des Betriebs und Testzugriff wahrend des Tests bereitzustellen. Ahnlichkeiten zwischen beiden Gebieten werden erfolgreich ausgenutzt und auf die Kombination einer effizienten Zustandsprufsumme mit einer effektiven Zustandsaktualisierung durch Bit-Flipping zuruckgefuhrt. Die durchgefuhrten Experimente fur offentlich verfugbare und industrielle Schaltungen beurteilen die vereinheitlichte Architektur in beiden Gebieten und zeigen eine verbesserte Flacheneffizienz, sowie eine erfolgreiche Korrektur wahrend der Fehlertoleranz. Fur die Testunterstutzung belegen die Ergebnisse Vorteile in Bezug auf Testzeit, Testdatenumfang, maximale und durchschnittliche Verlustleistung im Testbetrieb sowie Testenergie.

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