CCTorus : A New Torus Topology for Interconnection Networks

— The topology of interconnection networks plays a key role in the performance of all general purpose networking applications. Mesh, Torus, and Hypercube have been the most popular interconnection network topologies used in most of the digital communication systems. Among these topologies Torus is well suited in any general purpose networking application because of its simple network structure and high degree of symmetry. The performance of an interconnection network can be measured using various performance metrics as well as structural properties. Performance parameters that must be considered in designing an interconnection network are latency, throughput, cost, node degree, network diameters, and path diversity. Keeping these factors in mind, in this paper, we have proposed an interconnection network topology namely Centrally Connected Torus (CCTorus), which is the new version of classical Torus network. The aim is to achieve low latency, high throughput, minimum network diameter and better path diversity. In this paper the proposed topology is evaluated by using both theoretical analysis and simulations. Simulation results show that CCTorus has better scalability, and its average latency and average throughput is better than that of Mesh, XMesh, Torus, and XTorus by significant proportions respectively, particularly for larger size networks.

[1]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[2]  Kenneth J. Thurber,et al.  Interconnection networks: a survey and assessment , 1974, AFIPS '74.

[3]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[4]  Chao Zhang,et al.  P2i-torus: A hybrid artchitecutre for direct interconnection , 2011, Proceedings of 2011 International Conference on Computer Science and Network Technology.

[5]  Ki Hwan Yum,et al.  Design and Analysis of On-Chip Networks for Large-Scale Cache Systems , 2010, IEEE Transactions on Computers.

[6]  Javier Navaridas,et al.  Twisted Torus Topologies for Enhanced Interconnection Networks , 2010, IEEE Transactions on Parallel and Distributed Systems.

[8]  Wang Jue,et al.  Xtorus: An Extended Torus Topology for On-Chip Massive Data Communication , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

[9]  Feng Wei Networks on Chip Based on Diagonal Interlinked Mesh Topology Structure , 2009 .

[10]  Zhu Xiao,et al.  Xmesh: A Mesh-Like Topology for Network on Chip , 2007 .

[11]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .