Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories

[1]  Zahra Azad,et al.  ORIENT: Organized interleaved ECCs for new STT-MRAM caches , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Kaushik Roy,et al.  Approximate storage for energy efficient spintronic memories , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  Yiran Chen,et al.  CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[5]  Kartik Mohanram,et al.  Reliable Nonvolatile Memories: Techniques and Measures , 2017, IEEE Design & Test.

[6]  Nanning Zheng,et al.  Design techniques to improve the device write margin for MRAM-based cache memory , 2011, GLSVLSI '11.

[7]  Yiran Chen,et al.  Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM) , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Yiran Chen,et al.  Read Performance: The Newest Barrier in Scaled STT-RAM , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Hossein Asadi,et al.  ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches , 2019, ASP-DAC.

[10]  Myoungsoo Jung,et al.  Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory , 2014 .

[11]  Muhammad Shafique,et al.  AdAM: Adaptive approximation management for the non-volatile memory hierarchies , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Mehdi Baradaran Tahoori,et al.  Fault tolerant approximate computing using emerging non-volatile spintronic memories , 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

[13]  Chris H. Kim,et al.  A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies , 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

[14]  John L. Henning SPEC CPU2006 benchmark descriptions , 2006, CARN.

[15]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .

[16]  Nikil D. Dutt,et al.  QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs , 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[17]  Seyed Ghassem Miremadi,et al.  TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches , 2019, IEEE Transactions on Computers.

[18]  Kiyoung Choi,et al.  Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[19]  Seyed Ghassem Miremadi,et al.  An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors , 2017, IEEE Transactions on Parallel and Distributed Systems.

[20]  Seyed Ghassem Miremadi,et al.  LER: Least-Error-Rate Replacement Algorithm for Emerging STT-RAM Caches , 2016, IEEE Transactions on Device and Materials Reliability.

[21]  Kaushik Roy,et al.  Write-optimized reliable design of STT MRAM , 2012, ISLPED '12.

[22]  Yiran Chen,et al.  MLC STT-RAM design considering probabilistic and asymmetric MTJ switching , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[23]  Yiran Chen,et al.  A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[24]  B. Diény,et al.  Precessional spin-transfer switching in a magnetic tunnel junction with a synthetic antiferromagnetic perpendicular polarizer , 2012 .

[25]  Yiran Chen,et al.  Asymmetry of MTJ switching and its implication to STT-RAM designs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[26]  Cong Xu,et al.  NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[28]  Yiran Chen,et al.  Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[29]  Nikil D. Dutt,et al.  Quality-configurable memory hierarchy through approximation: special session , 2017, CASES.