论文信息 - Derivation of Minimal Test Sets for Monotonic Logic Circuits

Derivation of Minimal Test Sets for Monotonic Logic Circuits

It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.

Ramaswami Dandapani | R. Dandapani

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