Morphable hundred-core heterogeneous architecture for energy-aware computation

Given the increased demand for high performance and energy-aware computational platforms, an adaptive heterogeneous computing platform composed of 100+ cores is herein proposed. The platform is based on an aggregate of multiple processing clusters, each containing multiple processing cores, whose architectures are adapted, in execution time, to the instantaneous energy and performance constraints of the software application under execution. This adaptation is ensured by a sophisticated hypervisor engine, implemented as a software layer in the host computer, which keeps a permanent record of a broad set of performance counters, gathered from the execution of each core in the field-programmable gate array (FPGA), in order to dynamically determine the optimal heterogeneous mix of processor architectures that satisfy the considered constraints. By issuing convenient reconfiguration commands to the reconfiguration engine, implemented in a static portion of the FPGA, partial dynamical reconfiguration mechanisms ensure a runtime adaptation of the cores that integrate each cluster. When compared with static instantiations of the considered many-core processor architectures, the obtained experimental results show that significant gains can be obtained with the proposed adaptive computing platform, with performance speedups up to 9.5× , while offering reductions in terms of the consumed energy as high as 10×.

[1]  Michael G. Lorenz,et al.  Power Consumption Reduction Through Dynamic Reconfiguration , 2004, FPL.

[2]  Lieven Eeckhout,et al.  Scheduling heterogeneous multi-cores through performance impact estimation (PIE) , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[3]  Michael L. Scott,et al.  Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[4]  Antonio González,et al.  Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment , 2013, 2013 25th International Symposium on Computer Architecture and High Performance Computing.

[5]  Jason Cong,et al.  Energy-efficient scheduling on heterogeneous multi-core architectures , 2012, ISLPED '12.

[6]  David H. Albonesi,et al.  ReMAP: A Reconfigurable Heterogeneous Multicore Architecture , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[7]  Sanjay Ranka,et al.  Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  Li Zhao,et al.  QuickIA: Exploring heterogeneous architectures on real prototypes , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[9]  Rakesh Kumar,et al.  A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors , 2010, Int. J. Reconfigurable Comput..

[10]  George F. Riley,et al.  Round-robin Arbiter Design and Generation , 2002, 15th International Symposium on System Synthesis, 2002..

[11]  Hamid Sarbazi-Azad,et al.  Application-Aware Topology Reconfiguration for On-Chip Networks , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Reiner W. Hartenstein,et al.  Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing , 2002, Lecture Notes in Computer Science.

[13]  René van Leuken,et al.  MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[14]  Dheeraj Reddy,et al.  Bias scheduling in heterogeneous multi-core architectures , 2010, EuroSys '10.

[15]  Israel Koren,et al.  Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores , 2011, 2011 International Conference on Parallel Architectures and Compilation Techniques.

[16]  Katherine Compton,et al.  Kernel sharing on reconfigurable multiprocessor systems , 2008, 2008 International Conference on Field-Programmable Technology.

[17]  Ricardo Chaves,et al.  On-the-fly attestation of reconfigurable hardware , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[18]  Anantha Chandrakasan,et al.  ystem Shutdown and Other rchitectural Techniques for Energy rogrammable Computation , 1996 .

[19]  Sanjiva Prasad,et al.  ReKonf: A Reconfigurable Adaptive ManyCore Architecture , 2012, 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications.

[20]  Israel Koren,et al.  Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing , 2013, TODE.

[21]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE) , 2000, FPL.

[22]  Alessandro Forin,et al.  Combining multicore and reconfigurable instruction set extensions , 2010, FPGA '10.

[23]  Vijay Janapa Reddi,et al.  High-performance and energy-efficient mobile web browsing on big/little systems , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[24]  Vanchinathan Venkataramani,et al.  Hierarchical power management for asymmetric multi-core in dark silicon era , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).