Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture

[1]  David G. Chinnery,et al.  Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design , 2002 .

[2]  Kurt Keutzer,et al.  Reducing the Timing Overhead , 2004 .

[3]  Alberto L. Sangiovanni-Vincentelli,et al.  The best of both worlds: the efficient asynchronous implementation of synchronous specifications , 2004, Proceedings. 41st Design Automation Conference, 2004..

[4]  Ross Smith,et al.  Asynchronous design using commercial HDL synthesis tools , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[5]  Luciano Lavagno,et al.  Handshake protocols for de-synchronization , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[6]  Andrew Bardsley,et al.  Compiling the language Balsa to delay insensitive hardware , 1997 .

[7]  Stephen B. Furber,et al.  Scan testing of micropipelines , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[8]  Joep L. W. Kessels,et al.  The Tangram framework: asynchronous circuits for low power , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[9]  Yehea I. Ismail,et al.  Statistical static timing analysis: how simple can we get? , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[10]  Luciano Lavagno,et al.  A concurrent model for de-synchronization , 2003 .

[11]  Jim D. Garside,et al.  AMULET1: a micropipelined ARM , 1994, Proceedings of COMPCON '94.

[12]  Sani R. Nassif,et al.  The care and feeding of your statistical static timer , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[13]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[14]  Paul Day,et al.  Four-phase micropipeline latch control circuits , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Benoît Caillaud,et al.  From Synchrony to Asynchrony , 1999, CONCUR.

[16]  Jim D. Garside,et al.  AMULET3: a high-performance self-timed ARM microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[17]  Luciano Lavagno,et al.  Automated synthesis of micro-pipelines from behavioral Verilog HDL , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[18]  Marly Roncken,et al.  A fully asynchronous low-power error corrector for the DCC player , 1994 .

[19]  Marly Roncken,et al.  The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..

[20]  Amir Pnueli,et al.  Marked Directed Graphs , 1971, J. Comput. Syst. Sci..

[21]  Alex Kondratyev,et al.  Testing of asynchronous designs by "inappropriate" means. Synchronous approach , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[22]  Alberto L. Sangiovanni-Vincentelli,et al.  Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment , 2003, EMSOFT.

[23]  Jean-Christophe Le Lann,et al.  POLYCHRONY for System Design , 2003, J. Circuits Syst. Comput..

[24]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[25]  Ran Ginosar,et al.  A doubly-latched asynchronous pipeline , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[26]  Nicolas Halbwachs,et al.  Synchronous Programming of Reactive Systems , 1992, CAV.

[27]  Luciano Lavagno,et al.  From synchronous to asynchronous: an automatic approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[28]  Paul Wielage,et al.  Clock synchronization through handshake signalling , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[29]  William J. Dally,et al.  Low-latency plesiochronous data retiming , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[30]  Michael Kishinevsky,et al.  Performance Analysis Based on Timing Simulation , 1994, 31st Design Automation Conference.

[31]  V. Varshavsky,et al.  Logical timing (global synchronization of asynchronous arrays) , 1995, Proceedings the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis.

[32]  Ching-Yi Wang,et al.  An asynchronous 2-D discrete cosine transform chip , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[33]  Kees van Berkel,et al.  Handshake Circuits: An Asynchronous Architecture for VLSI Programming , 1993 .

[34]  Luciano Lavagno,et al.  Coping with the variability of combinational logic delays , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[35]  Mitchell A. Thornton,et al.  A coarse-grain phased logic CPU , 2005, IEEE Transactions on Computers.

[36]  Daniel H. Linder,et al.  Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry , 1996, IEEE Trans. Computers.