Synthesis of integer multipliers in sum of pseudoproducts form

We discuss the realization of two standard multiplier structures in a three-level form based on EXOR, called sum of pseudoproducts (SPP for short). SPP extends the classical two-level sum of products form (SOP). Our study focuses on the minimization of the number of gates and levels of the circuits needed to construct Wallace-type multipliers, and a 54 × 54-bit multiplier. The basic building blocks explicitly studied are the 4 × 4 parallel multiply module, and the family of carry-save adders Ci, with i input lines, that compose the Wallace trees. We show that the ratio of the number of gates of Ci in SPP over SOP decreases exponentially with i, being very small even for small values of i (ratio > 0.2 for i = 9). The evaluation of power, speed, and chip area with three different standard tools also shows the interest of the proposed approach.

[1]  Fabrizio Luccio,et al.  Fast three-level logic minimization based on autosymmetry , 2002, DAC '02.

[2]  Valentina Ciriani.  Synthesis of SPP three-level logic networks using affine spaces , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Robert K. Brayton,et al.  ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions , 1993, 30th ACM/IEEE Design Automation Conference.

[4]  Olivier Coudert,et al.  Doing two-level logic minimization 100 times faster , 1995, SODA '95.

[5]  Ahmad A. Hiasat,et al.  New Efficient Structure for a Modular Multiplier for RNS , 2000, IEEE Trans. Computers.

[6]  Yervant Zorian,et al.  An Effective Built-In Self-Test Scheme for Parallel Multipliers , 1999, IEEE Trans. Computers.

[7]  Rajendra S. Katti,et al.  Low Complexity Multiplication in a Finite Field Using Ring Representation , 2003, IEEE Trans. Computers.

[8]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[9]  Valentina Ciriani,et al.  Logic minimization using exclusive OR gates , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[10]  Fabrizio Luccio,et al.  Three-level logic minimization based on function regularities , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  H. T. Kung,et al.  The Area-Time Complexity of Binary Multiplication , 1981, JACM.

[12]  M.A. Hasan,et al.  New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases , 1998, IEEE Trans. Computers.

[13]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[14]  Graham A. Jullien,et al.  A New Design Technique for Column Compression Multipliers , 1995, IEEE Trans. Computers.

[15]  Fabrizio Luccio,et al.  On a New Boolean Function with Applications , 1999, IEEE Trans. Computers.

[16]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[17]  Saburo Muroga,et al.  Absolute Minimization of Completely Specified Switching Functions , 1991, IEEE Trans. Computers.

[18]  Michael J. Flynn,et al.  Technology Scaling Effects on Multipliers , 1998, IEEE Trans. Computers.

[19]  Kunihiro Asada,et al.  Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic , 1998 .

[20]  Hung Chi Lai,et al.  Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables , 1987, IEEE Transactions on Computers.

[21]  Paul A. Wintz,et al.  Fast Multipliers , 1970, IEEE Transactions on Computers.

[22]  Tsutomu Sasao,et al.  Representations of Logic Functions Using EXOR Operators , 1996 .