Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

We propose a timing-driven discrete cell-sizing algorithm that can address total cell size and/or leakage power constraints. We model cell sizing as a "discretized" mincost network flow problem, wherein available sizes of each cell are modeled as nodes. Flow passing through a node indicates the choice of the corresponding cell size, and the total flow cost reflects the timing objective function value corresponding to these choices. Compared to other discrete optimization methods for cell sizing, our method can obtain near-optimal solutions in a time-efficient manner. We tested our algorithm on ISCAS'85 benchmarks, and compared our results to those produced by an optimal dynamic programming- (DP-) based method. The results show that compared to the optimal method, the improvements to an initial sizing solution obtained by our method is only 1% (3%) worse when using a 180nm (90 nm) library, while being 40-60 times faster. We also obtained results for ISPD'12 cell-sizing benchmarks, under leakage power constraint, and compared them to those of a state-of-the-art approximate DP method (optimal DP runs out of memory for the smallest of these circuits). Our results show that we are only 0.9% worse than the approximate DP method, while being more than twice as fast.

[1]  Nimrod Megiddo,et al.  A simplex algorithm whose average number of steps is bounded between two quadratic functions of the smaller dimension , 1985, JACM.

[2]  Shantanu Dutt,et al.  Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous $V_{dd}$, $V_{th}$ Assignments, Gate Sizing, and Placement , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Ravindra K. Ahuja,et al.  Network Flows: Theory, Algorithms, and Applications , 1993 .

[4]  P. Kudva,et al.  Gate-size selection for standard cell libraries , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[5]  Ravindra K. Ahuja,et al.  The Scaling Network Simplex Algorithm , 1992, Oper. Res..

[6]  John P. Fishburn,et al.  TILOS: A posynomial programming approach to transistor sizing , 2003, ICCAD 2003.

[7]  Ulrich Brenner.  VLSI legalization with minimum perturbation by iterative augmentation , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Shiyan Hu,et al.  Gate Sizing for Cell-Library-Based Designs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Jochen A. G. Jess,et al.  Gate sizing in MOS digital circuits with linear programming , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[10]  Shantanu Dutt,et al.  Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Martin D. F. Wong,et al.  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[12]  Shantanu Dutt,et al.  A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Majid Sarrafzadeh,et al.  Timing-driven placement using design hierarchy guided constraint generation , 2002, ICCAD 2002.

[14]  Olivier Coudert,et al.  Gate sizing for constrained delay/power/area optimization , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[15]  S. Dutt,et al.  A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[16]  Panos M. Pardalos,et al.  A bilinear relaxation based algorithm for concave piecewise linear network flow problems , 2007 .

[17]  Jiang Hu,et al.  Gate sizing and device technology selection algorithms for high-performance industrial designs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[18]  Ravindra K. Ahuja,et al.  Network Flows , 2011 .

[19]  Shantanu Dutt,et al.  A Network-Flow Based Cell Sizing Algorithm , 2008 .

[20]  Shantanu Dutt,et al.  Timing yield optimization via discrete gate sizing using globally-informed delay PDFs , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Shantanu Dutt,et al.  Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.