Design of Radix Converters Using Arithmetic Decomposition

In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs.

[1]  Tsutomu Sasao Radix converters: complexity and implementation by LUT cascades , 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

[2]  T. Sasao Analysis and synthesis of weighted-sum functions , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Takafumi Aoki,et al.  Design and verification of parallel multipliers using arithmetic description language: ARITH , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

[4]  Tsutomu Sasao,et al.  Switching Theory for Logic Synthesis , 1999, Springer US.

[5]  I. Koren Computer arithmetic algorithms , 2018 .

[6]  Michitaka Kameyama,et al.  A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic , 1995 .

[7]  Saburo Muroga,et al.  VLSI system design , 1982 .