Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

With a great scalability potential, nonvolatile magnetoresistive memory with spin-torque transfer (STT) programming has become a topic of great current interest. This paper addresses cell structure design for STT magnetoresistive RAM, content addressable memory (CAM) and ternary CAM (TCAM). We propose a new RAM cell structure design that can realize high speed and reliable sensing operations in the presence of relatively poor magnetoresistive ratio, while maintaining low sensing current through magnetic tunneling junctions (MTJs). We further apply the same basic design principle to develop new cell structures for nonvolatile CAM, and TCAM. The effectiveness of the proposed RAM, CAM and TCAM cell structures has been demonstrated by circuit simulation at 0.18 ¿m CMOS technology.

[1]  N. Sakimura,et al.  MRAM Cell Technology for Over 500-MHz SoC , 2007, IEEE Journal of Solid-State Circuits.

[2]  H. Hoenigschmid,et al.  A high-speed 128-kb MRAM core for future universal memory applications , 2004, IEEE Journal of Solid-State Circuits.

[3]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4]  Yiran Chen,et al.  Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM) , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[5]  M. Aoki,et al.  A novel voltage sensing 1T/2MTJ cell with resistance ratio for highly stable and scalable MRAM , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[6]  E.K.S. Au,et al.  A novel current-mode sensing scheme for magnetic tunnel junction MRAM , 2004, IEEE Transactions on Magnetics.

[7]  Chang-gyu Hwang,et al.  Nanotechnology enables a new memory growth model , 2003 .

[8]  Kinam Kim,et al.  Memory Technologies for sub-40nm Node , 2007, 2007 IEEE International Electron Devices Meeting.

[9]  A. Omair,et al.  A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers , 2005, IEEE Journal of Solid-State Circuits.

[10]  Z. Diao,et al.  Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory , 2007 .

[11]  N. Kasai,et al.  A 16-Mb Toggle MRAM With Burst Modes , 2007, IEEE Journal of Solid-State Circuits.

[12]  Shoji Ikeda,et al.  2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[14]  J. Otani,et al.  A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[15]  YunSeung Shin,et al.  Non-volatile memory technologies for beyond 2010 , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[16]  H. Pon Technology scaling impact on NOR and NAND flash memories and their applications , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[17]  D. Dimitrov,et al.  Thermal fluctuation effects on spin torque induced switching: Mean and variations , 2008 .

[18]  S. Ikeda,et al.  2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read , 2008, IEEE Journal of Solid-State Circuits.