10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.

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[2]  Mau-Chung Frank Chang,et al.  A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface , 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

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[4]  Yusuf Leblebici,et al.  10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[5]  Jongsun Kim,et al.  An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling , 2012, IEEE Journal of Solid-State Circuits.