论文信息 - vMOS-based compressor designs

vMOS-based compressor designs

Partial-product reduction circuits (compressors) are of capital importance in the design of high performance parallel multipliers. This paper proposes compressor designs based on threshold gates which have been implemented as vMOS circuits. A typical block, a (4,2) compressor, is fully developed. Data for a (6,2) compressor are also provided. Results show that such compressors have the best performance in delay and power-delay product when compared to conventional implementations.

[1] M. Horowitz,et al. A Pipelined 64x64b Iterative Array Multiplier , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[2] Saburo Muroga,et al. Threshold logic and its applications , 1971 .

[3] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[4] G. De Micheli,et al. Circuit and architecture trade-offs for high-speed multiplication , 1991 .

[5] David Zhang,et al. VLSI compressor design with applications to digital neural networks , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[6] Gloria Huertas,et al. A practical floating-gate Muller-C element using vMOS threshold gates , 2001 .

[7] Tadashi Shibata,et al. A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[8] T. Noguchi,et al. A 15-ns 32*32-b CMOS multiplier with an improved parallel structure , 1990 .