Chung-Kuan Cheng

发表

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Study of visual stimulus waveforms via forced van der Pol oscillator model for SSVEP-based brain-computer interfaces

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

Fast adders in modern FPGAs

Jianhua Liu, Chung-Kuan Cheng, Michael Chang, 2004, FPGA '04.

Layer Minimization of Escape Routing in Area Array Packaging

Chung-Kuan Cheng, Renshen Wang, Rui Shi, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Tutorial on VLSI Partitioning

Chung-Kuan Cheng, Sao-Jie Chen, Chung-Kuan Cheng, 2000, VLSI Design.

On-chip power network optimization with decoupling capacitors and controlled-ESRs

Ling Zhang, Wenjian Yu, Xiang Hu, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control

Quan Chen, Chung-Kuan Cheng, Shih-Hung Weng, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Cluster refinement for block placement

Jin Xu, Chung-Kuan Cheng, Pei-Ning Guo, 1997, DAC.

Floorplanning with abutment constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Integr..

Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2013, 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Fast and Precise Routability Analysis with Conditional Design Rules

Chung-Kuan Cheng, Dongwon Park, Ilgweon Kang, 2018, 2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

A global router with a theoretical bound on the optimal solution

Chung-Kuan Cheng, Jianmin Li, IV RobertC.Carden, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Exploring the rogue wave phenomenon in 3D power distribution networks

Xiang Hu, Chung-Kuan Cheng, Peng Du, 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

Unified quadratic programming approach for mixed mode placement

Chung-Kuan Cheng, Bo Yao, Nan-Chi Chou, 2005, ISPD '05.

Performance-driven partitioning using retiming and replication

Chung-Kuan Cheng, Nan-Chi Chou, Walter H. Ku, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Efficient and accurate eye diagram prediction for high speed signaling

Yi Zhu, Wenjian Yu, Rui Shi, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Area minimization of power distribution network using efficient nonlinear programming techniques

Jun Gu, Xianlong Hong, Chung-Kuan Cheng, 2001, ICCAD 2001.

Circuit Partitioning for Huge Logic Emulation Systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1994, 31st Design Automation Conference.

The optimal partitioning of networks

Chung-Kuan Cheng, Chung-Kuan Cheng, 1992, Networks.

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Simultaneous routing and buffer insertion for high performance interconnect

Chung-Kuan Cheng, Ting-Ting Y. Lin, John Lillis, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization

Yi Zhu, Chung-Kuan Cheng, Haikun Zhu, 2007, 2007 Asia and South Pacific Design Automation Conference.

Enabling power distribution network analysis flows for 3D ICs

Xiang Hu, Chung-Kuan Cheng, Riko Radojcic, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

An optimal probe testing algorithm for the connectivity verification of MCM substrates

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1992, ICCAD.

A fast time-domain EM-TCAD coupled simulation framework via matrix exponential

Quan Chen, Lijun Jiang, Ngai Wong, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Design and implementation of a global router based on a new layout-driven timing model with three poles

Chung-Kuan Cheng, John Lillis, Fang-Jou Liu, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Network partitioning into tree hierarchies

Chung-Kuan Cheng, Lung-Tien Liu, Ming-Ter Kuo, 1996, DAC '96.

Power network analysis and optimization

Chung-Kuan Cheng, Wanping Zhang, 2009 .

Generalized volterra series model for highly nonlinear optical interconnects, circuits and devices

Chung-Kuan Cheng, Sadik C. Esener, Emel Yuceturk, 2007 .

Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response

Chung-Kuan Cheng, A. Deutsch, G. Katopis, 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders

Chung-Kuan Cheng, 2009, 2009 19th IEEE Symposium on Computer Arithmetic.

Advancing supercomputer performance through interconnection topology synthesis

Yi Zhu, Scott B. Baden, Chung-Kuan Cheng, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Efficient transient simulation for transistor-level analysis

Chung-Kuan Cheng, Ernest S. Kuh, Manjit Borah, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A buffer planning algorithm based on dead space redistribution

Yici Cai, Jun Gu, Sheqin Dong, 2003, ASP-DAC '03.

ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques

Chung-Kuan Cheng, Bill Lin, Sicun Gao, 2019, ISPD.

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

Andrew B. Kahng, Chung-Kuan Cheng, Ilgweon Kang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Rectilinear block placement using sequence-pair

Jin Xu, Chung-Kuan Cheng, Pei-Ning Guo, 1998, ISPD '98.

A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation

Quan Chen, Chung-Kuan Cheng, Shih-Hung Weng, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The Orientation of Modules Based on Graph Decomposition

Chung-Kuan Cheng, T. C. Hu, So-Zen Yao, 1991, IEEE Trans. Computers.

CAD transactions best paper award "Floorplanning using a tree representation"

Chung-Kuan Cheng, Pei-Ning Guo, T. Takahashi, 2002 .

Floorplanning algorithms for vlsi physical design automation

Chung-Kuan Cheng, Yingxin Pang, 2000 .

Toward better wireload models in the presence of obstacles

Andrew B. Kahng, Chung-Kuan Cheng, Dirk Stroobandt, 2002, IEEE Trans. Very Large Scale Integr. Syst..

A buffer planning algorithm with congestion optimization

Yici Cai, Jun Gu, Sheqin Dong, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation

Chung-Kuan Cheng, Peng Du, Shih-Hung Weng, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Floorplan representations: Complexity and connections

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2003, TODE.

MATEX: A distributed framework for transient simulation of power distribution networks

Chung-Kuan Cheng, Hao Zhuang, Shih-Hung Weng, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

A gradient method on the initial partition of Fiduccia-Mattheyses algorithm

Chung-Kuan Cheng, Lung-Tien Liu, Ming-Ter Kuo, 1995, ICCAD.

Cell-phone based Drowsiness Monitoring and Management system

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Symbolic layout compaction under conditional design rules

Chung-Kuan Cheng, Yuh-Zen Liao, So-Zen Yao, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Passive compensation for high performance inter-chip communication

Chung-Kuan Cheng, Chun-Chen Liu, Haikun Zhu, 2007, 2007 25th International Conference on Computer Design.

A network flow approach for hierarchical tree partitioning

Chung-Kuan Cheng, Ming-Ter Kuo, 1997, DAC.

Corner block list representation and its application to floorplan optimization

Yici Cai, Jun Gu, Sheqin Dong, 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

A buffer planning algorithm for chip-level floorplanning

Yici Cai, Jun Gu, Sheqin Dong, 2007, Science in China Series F: Information Sciences.

Power distribution network design optimization with on-die voltage-dependent leakage path

Yang Liu, Chung-Kuan Cheng, Xiang Zhang, 2013, 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems.

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

Jianhua Liu, Chung-Kuan Cheng, John Lillis, 2007, 2007 Asia and South Pacific Design Automation Conference.

A study of pipelined pseudo-exhaustive testing on VLSI circuits with feedback

Chung-Kuan Cheng, Huoy-Yu Liou, T.-T.Y. Lin, 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

Buffer allocation algorithm with consideration of routing congestion

Jun Gu, Sheqin Dong, Chung-Kuan Cheng, 2004 .

EARLY FEASIBILITY AND COST ASSESSMENT FOR MULTICHIP MODULE TECHNOLOGIES

Chung-Kuan Cheng, Robert Clinton Carden, 1995 .

Buffer allocation algorithm with consideration of routing congestion

Yici Cai, Jun Gu, Sheqin Dong, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

More realistic power grid verification based on hierarchical current and power constraints

Ngai Wong, Andrew B. Kahng, Chung-Kuan Cheng, 2011, ISPD '11.

Block placement with symmetry constraints based on the O-tree non-slicing representation

Chung-Kuan Cheng, Florin Balasa, Koen Lampaert, 2000, DAC.

Timing optimization for multi-source nets

Chung-Kuan Cheng, John Lillis, Chung-Kuan Cheng, 1997, DAC 1997.

Reliability aware through silicon via planning for 3D stacked ICs

Xiaoming Chen, Wenjian Yu, Xiang Hu, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Constructing zero-deficiency parallel prefix adder of minimum depth

Chung-Kuan Cheng, Haikun Zhu, R. Graham, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Realizable parasitic reduction using generalized Y-Δ transformation

Chung-Kuan Cheng, Zhanhai Qin, Chung-Kuan Cheng, 2003, DAC.

A wire length estimation technique utilizing neighborhood density equations

Chung-Kuan Cheng, Paul M. Chau, Takeo Hamada, 1992, DAC '92.

Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing

Chung-Kuan Cheng, Lung-Tien Liu, Ting-Ting Lin, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Stairway compaction using corner block list and its applications with rectilinear blocks

Yici Cai, Jun Gu, Sheqin Dong, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

On-chip global clock distribution using directional rotary traveling-wave oscillator

Chung-Kuan Cheng, James F. Buckwalter, Yulei Zhang, 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

Optimal buffered clock tree synthesis

Chung-Kuan Cheng, Jae Chung, 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

Bus via reduction based on floorplan revising

Satoshi Goto, Sheqin Dong, Chung-Kuan Cheng, 2010, GLSVLSI '10.

Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, DAC '01.

Efficient escape routing for hexagonal array of high density I/Os

Rui Shi, Chung-Kuan Cheng, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A building block placement tool

Chung-Kuan Cheng, Jonathan Dufour, Robert McBride, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Analyzing High-Density ECG Signals Using ICA

Tzyy-Ping Jung, Yi Zhu, Chung-Kuan Cheng, 2008, IEEE Transactions on Biomedical Engineering.

On-chip bus signaling using passive compensation

Chung-Kuan Cheng, Yulei Zhang, A. Deutsch, 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

Floorplan Representation in VLSI

Chung-Kuan Cheng, Bo Yao, Zhou Feng, 2004 .

Proceedings of the 11th international workshop on System level interconnect prediction

Chung-Kuan Cheng, Sherief Reda, 2009 .

PAPER Special Section on VLSI Design and CAD Algorithms Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration

Masanori Hashimoto, Nonmembers, Chung-Kuan Cheng, 2008 .

Eye prediction of digital driver with power distribution network noise

Tzong-Lin Wu, Chung-Kuan Cheng, Chiu-Chih Chou, 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

Advancing supercomputer performance through interconnection topology synthesis

Yi Zhu, Scott B. Baden, Chung-Kuan Cheng, 2008, ICCAD 2008.

Character design and stamp algorithms for Character Projection Electron-Beam Lithography

Ronald L. Graham, Chung-Kuan Cheng, Peng Du, 2012, 17th Asia and South Pacific Design Automation Conference.

Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures

Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Noise minimization during power-up stage for a multi-domain power network

Yi Zhu, Wenjian Yu, Chung-Kuan Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

ECBL: an extended corner block list with solution space including optimum placement

Jun Gu, Shuo Zhou, Sheqin Dong, 2001, ISPD '01.

Timing optimization for multisource nets: characterization andoptimal repeater insertion

Chung-Kuan Cheng, John Lillis, Chung-Kuan Cheng, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High-speed and low-power on-chip global link using continuous-time linear equalizer

Chung-Kuan Cheng, James F. Buckwalter, Yulei Zhang, 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

On the bound of time-domain power supply noise based on frequency-domain target impedance

Xiang Hu, Chung-Kuan Cheng, Peng Du, 2009, SLIP '09.

Dynamic probe scheduling optimization for MCM substrate test

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Russell, 1994 .

An unconditional stable general operator splitting method for transistor level transient analysis

Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Distortion Minimization for Packaging Level Interconnects

Chung-Kuan Cheng, Hongyu Chen, Rui Shi, 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

An algorithmic framework for efficient large-scale circuit simulation using exponential integrators

Wenjian Yu, Chung-Kuan Cheng, Hao Zhuang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Area efficient pipelined pseudo-exhaustive testing with retiming

Chung-Kuan Cheng, Ting-Ting Y. Lin, Huoy-Yu Liou, 1996, DAC '96.

Impulse response generation from S-parameters for power delivery network simulation

Chung-Kuan Cheng, Ilgweon Kang, Xinan Wang, 2015, 2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity.

Tree Structures and Algorithms for Physical Design

Ronald L. Graham, Chung-Kuan Cheng, Dongwon Park, 2018, ISPD.

Algorithms for performance-driven design of integrated circuits

Chung-Kuan Cheng, John Lillis, Chung-Kuan Cheng, 1996 .

Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design

Wenjian Yu, Rui Shi, Chung-Kuan Cheng, 2009, IEICE Trans. Electron..

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals

Ling Zhang, Chung-Kuan Cheng, Bo Yao, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Multiple-level partitioning: an application to the very large-scale hardware simulator

Chung-Kuan Cheng, Y.-C. Wei, Z. Wurman, 1991 .

Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration

Masanori Hashimoto, Chung-Kuan Cheng, Akira Tsuchiya, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Balancing the interconnect topology for arrays of processors between cost and power

Feng Zhou, Ronald L. Graham, Chung-Kuan Cheng, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Research on floorplanning

Chung-Kuan Cheng, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

A mulitple level network approach for clock skew minimization with process variations

Chung-Kuan Cheng, Bo Yao, Hongyu Chen, 2004 .

Low power passive equalizer optimization using tritonic step response

Ling Zhang, Wenjian Yu, Chung-Kuan Cheng, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Exploring 3D power distribution network physics

Xiang Hu, Chung-Kuan Cheng, Peng Du, 2011, 2011 9th IEEE International Conference on ASIC.

An efficient multi-level placement technique using hierarchical partitioning

Chung-Kuan Cheng, T. Hamada, P. M. Chau, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

Modeling and Analysis of Power Distribution Networks in 3-D ICs

Xiang Hu, Chung-Kuan Cheng, James F. Buckwalter, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

VLSI block placement with alignment constraints based on corner block list

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Rui Shi, Chung-Kuan Cheng, Hongyu Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

A hierarchical three-way interconnect architecture for hexagonal processors

Feng Zhou, Ronald L. Graham, Chung-Kuan Cheng, 2003, SLIP '03.

A new layout-driven timing model for incremental layout optimization

Chung-Kuan Cheng, John Lillis, Fang-Jou Liu, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing

Andrew B. Kahng, Ion I. Mandoiu, Chung-Kuan Cheng, 2003, SLIP '03.

The mapping of logic designs into a very large scale hardware simulator

Chung-Kuan Cheng, Z. Wurman, Y.-C. Wei, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

On-chip high performance signaling using passive compensation

Masanori Hashimoto, Ling Zhang, Chung-Kuan Cheng, 2008, 2008 IEEE International Conference on Computer Design.

Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning

Xiang Hu, Chung-Kuan Cheng, Peng Du, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Performance-Driven Steiner Tree Algorithms for Global Routing

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1993, 30th ACM/IEEE Design Automation Conference.

FPGA global routing architecture optimization using a multicommodity flow approach

Yi Zhu, Chung-Kuan Cheng, Michael Bedford Taylor, 2007, 2007 25th International Conference on Computer Design.

Maximum concurrent flows and minimum cuts

Chung-Kuan Cheng, T. C. Hu, Chung-Kuan Cheng, 1992, Algorithmica.

Timing-power optimization for mixed-radix Ling adders by integer linear programming

Yi Zhu, Jianhua Liu, Chung-Kuan Cheng, 2008, 2008 Asia and South Pacific Design Automation Conference.

The Y architecture for on-chip interconnect: analysis and methodology

Andrew B. Kahng, Ion I. Mandoiu, Chung-Kuan Cheng, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Sequence-pair approach for rectilinear module placement

Jin Xu, Chung-Kuan Cheng, Pei-Ning Guo, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Circuit clustering using a stochastic flow injection method

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimal Test Size and Efficient Probe Scheduling for Substrate Verification Using Two-Probe Testers

Chung-Kuan Cheng, Nan-Chi Chou, 1993 .

Finite state machine decomposition for I/O minimization

Chung-Kuan Cheng, Lung-Tien Liu, Ming-Ter Kuo, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Novel Differential-Mode Equalizer With Broadband Common-Mode Filtering for Gb/s Differential-Signal Transmission

Tzong-Lin Wu, Chung-Kuan Cheng, Yu-Jen Cheng, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Layer Minimization of Escape Routing in Area Array Packaging

Rui Shi, Chung-Kuan Cheng, Renshen Wang, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Design methodology of high performance on-chip global interconnect using terminated transmission-line

Ling Zhang, Chung-Kuan Cheng, Ernest S. Kuh, 2009, 2009 10th International Symposium on Quality Electronic Design.

Measuring Steady-State Visual Evoked Potentials from non-hair-bearing areas

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2012, 2012 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

Prediction of high-performance on-chip global interconnection

Xiang Hu, Chung-Kuan Cheng, James F. Buckwalter, 2009, SLIP '09.

From Circuit Theory, Simulation to SPICEDiego<\/sup>: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits

Chung-Kuan Cheng, Quan Chen, Xinyuan Wang, 2016, IEEE Circuits and Systems Magazine.

Power line communication for hybrid power/signal pin SOC design

Yang Liu, Xiang Zhang, Chung-Kuan Cheng, 2015, 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Globally stable, highly parallelizable fast transient circuit simulation via faber series

Quan Chen, Ngai Wong, Chung-Kuan Cheng, 2012, 10th IEEE International NEWCAS Conference.

3-D floorplanning using labeled tree and dual sequences

Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, 2008, ISPD '08.

Prediction and Comparison of High-Performance On-Chip Global Interconnection

Xiang Hu, Chung-Kuan Cheng, James F. Buckwalter, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast evaluation of Bounded Slice-line Grid

Jun Gu, Sheqin Dong, Xianlong Hong, 2004, Journal of Computer Science and Technology.

Dynamic global buffer planning optimization based on detail block locating and congestion analysis

Yici Cai, Jun Gu, Sheqin Dong, 2003, DAC '03.

3D stacked power distribution considering substrate coupling

Xiaoming Chen, Xiang Hu, Chung-Kuan Cheng, 2009, 2009 IEEE International Conference on Computer Design.

Optimal wire sizing and buffer insertion for low power and a generalized delay model

Chung-Kuan Cheng, Ting-Ting Y. Lin, John Lillis, 1995, ICCAD.

Integrated algorithmic logical and physical design of integer multiplier

Jianhua Liu, Shuo Zhou, Chung-Kuan Cheng, 2005, ASP-DAC.

An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits

Quan Chen, Chung-Kuan Cheng, Wim Schoenmaker, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A multi-level transmission line network approach for multi-giga hertz clock distribution

Chung-Kuan Cheng, Hongyu Chen, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization

Andrew A. Chien, Yi Zhu, Chung-Kuan Cheng, 2005, 2005 International Conference on Computer Design.

Performance-Driven Partitioning Using a Replication Graph Approach

Chung-Kuan Cheng, T. C. Hu, Lung-Tien Liu, 1995, 32nd Design Automation Conference.

A non-slicing floorplanning algorithm using corner block list topological representation

Yici Cai, Jun Gu, Sheqin Dong, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Solving the net matching problem in high-performance chip design

Masahiro Fujita, Chung-Kuan Cheng, Ramamohan Paturi, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ePlace-3D: Electrostatics based Placement for 3D-ICs

Chung-Kuan Cheng, Hao Zhuang, Pengwen Chen, 2015, ISPD.

An O(nloglogn) algorithm for evaluation of Bounded Slice-line Grid

Jun Gu, Sheqin Dong, Xianlong Hong, 2003, ASICON 2003.

Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph

Andrew B. Kahng, Chung-Kuan Cheng, Peng Du, 2012, ISPD '12.

Efficient Power Network Analysis with Modeling of Inductive Effects

Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Adaptive Sensitivity Analysis with Nonlinear Power Load Modeling

Chung-Kuan Cheng, Yuwei Wang, Po-Ya Hsu, 2018, 2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Linear Dropout Regulator based power distribution design under worst loading

Wenjian Yu, Xiang Hu, Chung-Kuan Cheng, 2011, 2011 9th IEEE International Conference on ASIC.

A multi-level transmission line network approach for multi-giga hertz clock distribution

Chung-Kuan Cheng, Hongyu Chen, 2005, ASP-DAC.

Floorplanning using a tree representation

Takeshi Yoshimura, Chung-Kuan Cheng, Toshihiko Takahashi, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Arbitrary convex and concave rectilinear block packing based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An Algorithmic Approach for Generic Parallel Adders

Jianhua Liu, Shuo Zhou, Chung-Kuan Cheng, 2003, ICCAD.

Optimal wire sizing and buffer insertion for low power and a generalized delay model

Chung-Kuan Cheng, John Lillis, T.-T.Y. Lin, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Optimization of power dissipation and skew sensitivity in clock buffer synthesis

De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1995, ISLPED '95.

On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design

Chung-Kuan Cheng, Renshen Wang, 2009, GLSVLSI '09.

An efficient multilevel placement technique using hierarchical partitioning

Chung-Kuan Cheng, T. Hamada, P. M. Chau, 1992 .

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Yici Cai, Qiang Zhou, Zhuoyuan Li, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

General Floorplans with L/T-Shaped Blocks Using Corner Block List

Jun Gu, Sheqin Dong, Xianlong Hong, 2006, Journal of Computer Science and Technology.

Extending moment computation to 2-port circuit representations

Chung-Kuan Cheng, Fang-Jou Liu, 1998, DAC.

Circuit simulation via matrix exponential method for stiffness handling and parallel processing

Quan Chen, Ngai Wong, Chung-Kuan Cheng, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration

Masanori Hashimoto, Chung-Kuan Cheng, Akira Tsuchiya, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals

Ling Zhang, Chung-Kuan Cheng, Bo Yao, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Floorplan Representation in VLSI

Chung-Kuan Cheng, Bo Yao, Zhou Feng, 2004, Handbook of Data Structures and Applications.

An optimal probe testing algorithm for the connectivity verification of MCM substrates

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method

Chung-Kuan Cheng, Chin-Chih Chang, Chin-Chi Teng, 2015, TODE.

An enhanced perturbing algorithm for floorplan design using the O-tree representation

Takeshi Yoshimura, Chung-Kuan Cheng, Yingxin Pang, 2000, ISPD '00.

Linear decomposition algorithm for VLSI design applications

Chung-Kuan Cheng, John Lillis, Jianmin Li, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

An on-chip global broadcast network design with equalized transmission lines in the 1024-core era

Guang Sun, Lieguang Zeng, Chung-Kuan Cheng, 2012, SLIP '12.

Placement and beyond in honor of Ernest S. Kuh

Chung-Kuan Cheng, 2011, ISPD '11.

Session details: Low power design for FPGAs

Lei He, Chung-Kuan Cheng, 2005, ISLPED '05.

Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks

Yici Cai, Jun Gu, Sheqin Dong, 2002, TODE.

A general purpose multiple way partitioning algorithm

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1991, 28th ACM/IEEE Design Automation Conference.

Timing model reduction for hierarchical timing analysis

Yi Zhu, Shuo Zhou, Ronald L. Graham, 2006, ICCAD.

3D floorplan representations: Corner links and partial order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Module Placement Based on Resistive Network Optimization

Chung-Kuan Cheng, Ernest S. Kuh, 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Timing optimization for multisource nets

Chung-Kuan Cheng, John Lillis, 1999 .

A compact algorithm for placement design using corner block list representation

Jun Gu, Sheqin Dong, Xianlong Hong, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

Static timing analysis in vlsi design

Shuo Zhou, Chung-Kuan Cheng, 2006 .

VLSI Block Placement With Alignment Constraints

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings

Chung-Kuan Cheng, Sherief Reda, 2009, SLIP.

Block-oriented programmable design with switching network interconnect

Chingwei Yeh, Chung-Kuan Cheng, T. C. Hu, 1994, IEEE Trans. Very Large Scale Integr. Syst..

A performance-driven I/O pin routing algorithm

Dongsheng Wang, Arunabha Sen, Chung-Kuan Cheng, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2018, ACM Trans. Design Autom. Electr. Syst..

Clock Skew Analysis via Vector Fitting in Frequency Domain

Ling Zhang, Wenjian Yu, Chung-Kuan Cheng, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Efficient transient simulation for transistor-level analysis

Chung-Kuan Cheng, Zhengyong Zhu, E.S. Kuh, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A probabilistic multicommodity-flow solution to circuit clustering problems

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1992, ICCAD.

Geometric compaction on channel routing

Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Towards efficient hierarchical designs by ratio cut partitioning

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

RCLK-VJ network reduction with Hurwitz polynomial approximation

Chung-Kuan Cheng, Zhanhai Qin, 2003, ASP-DAC '03.

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing

Yici Cai, Jun Gu, Xianlong Hong, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Predicting the worst-case voltage violation in a 3D power network

Wenjian Yu, Xiang Hu, Chung-Kuan Cheng, 2009, SLIP '09.

Performance driven multiple-source bus synthesis using buffer insertion

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, 1995, ASP-DAC '95.

Power grid simulation using matrix exponential method with rational Krylov subspaces

Chung-Kuan Cheng, Hao Zhuang, Shih-Hung Weng, 2013, 2013 IEEE 10th International Conference on ASIC.

Worst-case noise prediction using power network impedance profile

Yang Liu, Xiang Zhang, Chung-Kuan Cheng, 2013, 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Physical models and algorithms for optoelectronic MCM layout

Chung-Kuan Cheng, S. H. Lee, Jiao Fan, 1995, IEEE Trans. Very Large Scale Integr. Syst..

A general purpose multiple way partitioning algorithm

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1991, DAC '91.

An iterative division algorithm for FPGAs

Jianhua Liu, Chung-Kuan Cheng, Michael Chang, 2006, FPGA '06.

Energy and switch area optimizations for FPGA global routing architectures

Yi Zhu, Chung-Kuan Cheng, Michael Bedford Taylor, 2009, TODE.

Efficient power network analysis with complete inductive modeling

Jian Wang, Wenjian Yu, Xianlong Hong, 2009, 2009 10th International Symposium on Quality Electronic Design.

Skew sensitivity minimization of buffered clock tree

Jae Chung, Chung-Kuan Cheng, Chung-Kuan Cheng, 1994, ICCAD '94.

Circuit simulation using matrix exponential method

Quan Chen, Chung-Kuan Cheng, Shih-Hung Weng, 2011, 2011 9th IEEE International Conference on ASIC.

Transient Circuit Simulation for Differential Algebraic Systems using Matrix Exponential

Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

On the construction of zero-deficiency parallel prefix circuits with minimum depth

Ronald L. Graham, Chung-Kuan Cheng, Haikun Zhu, 2006, TODE.

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2010, ISPD '10.

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2006, Asia and South Pacific Conference on Design Automation, 2006..

The Y-Architecture for On-Chip Interconnect: Analysis and Methodology

Andrew B. Kahng, Ion I. Mandoiu, Chung-Kuan Cheng, 2003, ICCAD.

Optimal planning for mesh-based power distribution

Andrew B. Kahng, Chung-Kuan Cheng, Hongyu Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Optimization by iterative improvement: an experimental evaluation on two-way partitioning

Chingwei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient algorithm for the net matching problem

Masahiro Fujita, Chung-Kuan Cheng, Robert J. Carragher, 1993, ICCAD.

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?

Fook-Luen Heng, Andrew B. Kahng, Vijay Pitchumani, 2005, ASP-DAC.

Theory and Algorithms of Physical Design

Andrew B. Kahng, Chung-Kuan Cheng, T. C. Hu, 2018, ISPD.

Corner block list representation and its application with boundary constraints

Yici Cai, Jun Gu, Sheqin Dong, 2004, Science in China Series F: Information Sciences.

Routability improvement using dynamic interconnect architecture

Chung-Kuan Cheng, Jianmin Li, 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

VLSI floorplanning with boundary constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, ASP-DAC '01.

Contemporary data path design optimization

Jianhua Liu, Chung-Kuan Cheng, 2006 .

A replication cut for two-way partitioning

Chung-Kuan Cheng, T. C. Hu, Lung-Tien Liu, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing

Jun Gu, Xianlong Hong, Chung-Kuan Cheng, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power network analysis using an adaptive algebraic multigrid approach

Chung-Kuan Cheng, Bo Yao, Zhengyong Zhu, 2003, DAC '03.

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

Takumi Okamoto, Chung-Kuan Cheng, Renshen Wang, 2009, 2009 IEEE International Conference on Computer Design.

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Qiang Zhou, Zhuoyuan Li, Vijay Pitchumani, 2006, ISPD '06.

On general zero-skew clock net construction

Chung-Kuan Cheng, Nan-Chi Chou, 1995, IEEE Trans. Very Large Scale Integr. Syst..

A two-level two-way partitioning algorithm

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints

Ngai Wong, Xiang Hu, Chung-Kuan Cheng, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects

Chung-Kuan Cheng, James F. Buckwalter, Yulei Zhang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

3D power distribution network co-design for nanoscale stacked silicon ICs

Chung-Kuan Cheng, Wanping Zhang, Xiaoming Chen, 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

Digital design and programmable logic boards: Do students actually learn more?

Yi Zhu, Chung-Kuan Cheng, T. Weng, 2008, 2008 38th Annual Frontiers in Education Conference.

Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach

Chung-Kuan Cheng, Paul M. Chau, Takeo Hamada, 1993, 30th ACM/IEEE Design Automation Conference.

Two-Stage Newton-Raphson Method for Transistor-Level Simulation

Chung-Kuan Cheng, Ernest S. Kuh, Manjit Borah, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A block-diagonal structured model reduction scheme for power grid networks

Ngai Wong, Xiang Hu, Chung-Kuan Cheng, 2011, 2011 Design, Automation & Test in Europe.

Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness

Evangeline F. Y. Young, Chung-Kuan Cheng, Renshen Wang, 2010, TODE.

Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards

Yi Zhu, Thomas Weng, Chung-Kuan Cheng, 2009, IEEE Transactions on Education.

A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation

Chung-Kuan Cheng, Xiaodong Yang, Walter H. Ku, 2000, ASP-DAC.

Session details: Session 1C: Interconnect planning

Chung-Kuan Cheng, Robi Dutta, 2001, ICCAD 2001.

Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation

Chung-Kuan Cheng, Xinyuan Wang, Hao Zhuang, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Revisiting floorplan representations

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2001, ISPD '01.

Worst-case noise area prediciton of on-chip power distribution network

Yang Liu, Xiang Zhang, Chung-Kuan Cheng, 2014, 2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Fast Transient Simulation of Lossy Transmission Lines

Chung-Kuan Cheng, He Peng, 2007, 2007 IEEE International Symposium on Circuits and Systems.

High performance current-mode differential logic

Masanori Hashimoto, Jianhua Liu, Ling Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Buffer planning as an Integral part of floorplanning with consideration of routing congestion

Jun Gu, Sheqin Dong, Xianlong Hong, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

FARM: an efficient feed-through pin assignment algorithm

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

ePlace: Electrostatics based placement using Nesterov's method

Chung-Kuan Cheng, Chin-Chih Chang, Chin-Chi Teng, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

An unconditional stable general operator splitting method for transistor level

Chung-Kuan Cheng, Ernest S. Kuh, Zhengyong Zhu, 2006 .

Evaluating a bounded slice-line grid assignment in O(nlogn) time

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An O-tree representation of non-slicing floorplan and its applications

Takeshi Yoshimura, Chung-Kuan Cheng, Pei-Ning Guo, 1999, DAC '99.

Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction

Feng Zhou, Chung-Kuan Cheng, Hongyu Chen, 2002, SLIP '02.

Buffer planning algorithm based on partial clustered floorplanning

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, Sixth international symposium on quality electronic design (isqed'05).

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Chung-Kuan Cheng, Ting-Ting Y. Lin, John Lillis, 1996, DAC '96.

Finite state machine partitioning for I/O-limited design

Chung-Kuan Cheng, Lung-Tien Liu, Ming-Ter Kuo, 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.

Parallel transistor level full-chip circuit simulation

Chung-Kuan Cheng, He Peng, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Representing topological structures for 3-D floorplanning

Chung-Kuan Cheng, Renshen Wang, Evangeline F.Y. Young, 2009, 2009 International Conference on Communications, Circuits and Systems.

A buffer planning algorithm with congestion optimization

Jun Gu, Sheqin Dong, Xianlong Hong, 2004 .

TIGER: an efficient timing-driven global router for gate array and standard cell layout design

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Toward better wireload models in the presence of obstacles

Andrew B. Kahng, Chung-Kuan Cheng, Dirk Stroobandt, 2001, ASP-DAC '01.

RLC interconnect delay estimation via moments of amplitude and phase response

Chung-Kuan Cheng, Xiaodong Yang, Walter H. Ku, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Ancestor tree for arbitrary multi-terminal cut functions

Chung-Kuan Cheng, T. C. Hu, Chung-Kuan Cheng, 1990, IPCO.

Floorplan and placement approaches for vlsi physical design

Chung-Kuan Cheng, Pei-Ning Guo, Chung-Kuan Cheng, 1998 .

Octilinear redistributive routing in bump arrays

Chung-Kuan Cheng, Renshen Wang, 2009, GLSVLSI '09.

Parallel full-chip transient simulation at transistor level

Chung-Kuan Cheng, He Peng, K. Rouz, 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

Fast postplacement optimization using functional symmetries

Bo Hu, Malgorzata Marek-Sadowska, Kai Wang, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interconnect implications of growth-based structural models for VLSI circuits

Andrew B. Kahng, Chung-Kuan Cheng, Bao Liu, 2001, SLIP '01.

Skew Sensitivity Minimization Of Buffered Clock Tree

Chung-Kuan Cheng, Jae Chung, Chung-Kuan Cheng, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning

Qiang Zhou, Zhuoyuan Li, Wenjian Yu, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Worst-case performance prediction under supply voltage and temperature variation

Andrew B. Kahng, Chung-Kuan Cheng, Kambiz Samadi, 2010, SLIP '10.

A higher-order moment model for multiport circuits

Chung-Kuan Cheng, Fang-Jou Liu, 1999 .

Power grid sizing via convex programming

Xiang Hu, Chung-Kuan Cheng, Peng Du, 2011, 2011 9th IEEE International Conference on ASIC.

Communication latency aware low power NoC synthesis

Yi Zhu, Ronald L. Graham, Chung-Kuan Cheng, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Bill Salefski, Chung-Kuan Cheng, Nan-Chi Chou, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Timing Model Reduction for Hierarchical Timing Analysis

Yi Zhu, Chung-Kuan Cheng, R. Graham, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

An adaptive parallel flow for power distribution network simulation using discrete Fourier transform

Xiang Hu, Chung-Kuan Cheng, Peng Du, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Incremental Power Impedance Optimization Using Vector Fitting Modeling

Chung-Kuan Cheng, Wanping Zhang, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Physical planning of on-chip interconnect architectures

Feng Zhou, Chung-Kuan Cheng, Bo Yao, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

High-performance microelectronic substrate verification using probe testers

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Russell, 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

Data Flow Partitioning for Clock Period and Latency Minimization

Chung-Kuan Cheng, Lung-Tien Liu, Minshine Shih, 1994, 31st Design Automation Conference.

Low Power Passive Equalizer Design for Computer Memory Links

Ling Zhang, Wenjian Yu, Chung-Kuan Cheng, 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs

Chung-Kuan Cheng, Hao Zhuang, Kambiz Samadi, 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

Optimal and efficient buffer insertion and wire sizing

Chung-Kuan Cheng, John Lillis, T.-T.Y. Lin, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Timing optimization for multi-source nets: characterization and optimal repeater insertion

Chung-Kuan Cheng, John Lillis, 1997, DAC.

Corner block list: an effective and efficient topological representation of non-slicing floorplan

Yici Cai, Jun Gu, Sheqin Dong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Improving the efficiency of static timing analysis with false paths

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Noninvasive Study of the Human Heart using Independent Component Analysis

Tzyy-Ping Jung, Yi Zhu, Chung-Kuan Cheng, 2006, Sixth IEEE Symposium on BioInformatics and BioEngineering (BIBE'06).

Local ratio cut and set covering partitioning for huge logic emulation systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A multi-probe approach for MCM substrate testing

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Chung-Kuan Cheng, Hongliang Chang, Hao Zhuang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient frequency-dependent reluctance extraction for large-scale Power/Ground grid

Wenjian Yu, Xianlong Hong, Zeyi Wang, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

An interdigitated non-contact ECG electrode for impedance compensation and signal restoration

Chia-Hung Liu, Hao Liu, Chung-Kuan Cheng, 2015, 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Constructing zero-deficiency parallel prefix adder of minimum depth

Ronald L. Graham, Chung-Kuan Cheng, Haikun Zhu, 2005, ASP-DAC.

FFTPL: An analytic placement algorithm using fast fourier transform for density equalization

Chung-Kuan Cheng, Chin-Chih Chang, Chin-Chi Teng, 2013, 2013 IEEE 10th International Conference on ASIC.

Efficient Timing Analysis With Known False Paths Using Biclique Covering

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Routability improvement using dynamic interconnect architecture

Chung-Kuan Cheng, Jianmin Li, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Performance constrained floorplanning based on partial clustering [IC layout]

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Performance prediction of throughput-centric pipelined global interconnects with voltage scaling

Chung-Kuan Cheng, James F. Buckwalter, Yulei Zhang, 2010, SLIP '10.

Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications

Rui Shi, Chung-Kuan Cheng, Hongyu Chen, 2005, 2005 International Conference on Computer Design.

Boosting off-chip interconnects through power line communication

Chung-Kuan Cheng, Xiang Zhang, Ryan Coutts, 2016, 2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS).

The Y-architecture: yet another on-chip interconnect solution

Feng Zhou, Chung-Kuan Cheng, Bo Yao, 2003, ASP-DAC '03.

Simple tree-construction heuristics for the fanout problem

Masahiro Fujita, Chung-Kuan Cheng, Robert J. Carragher, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Linear placement algorithms and applications to VLSI design

Chung-Kuan Cheng, Chung-Kuan Cheng, 1987, Networks.

Linear decomposition algorithm for VLSI design applications

Chung-Kuan Cheng, Jianmin Li, John Lillis, 1995, ICCAD.

A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Satoshi Goto, Sheqin Dong, Chung-Kuan Cheng, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints"

Xiang Hu, Chung-Kuan Cheng, Yuanzhe Wang, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Layer minimization in escape routing for staggered-pin-array PCBs

Yao-Wen Chang, Chung-Kuan Cheng, Xin-Wei Shih, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Parallel transistor level circuit simulation using domain decomposition methods

Chung-Kuan Cheng, He Peng, Chung-Kuan Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

Ratio cut partitioning for hierarchical designs

Chung-Kuan Cheng, Yen-Chuen A. Wei, Chung-Kuan Cheng, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Solving the Net Matching Pro erforrnance Chip Desi

Chung-Kuan Cheng, Ramamohan Paturi, Masahiro Fujita, 1996 .

BDD-based logic partitioning for sequential circuits

Chung-Kuan Cheng, M. Fujita, M.-T. Kuo, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Hurwitz stable reduced order modeling for RLC interconnect trees

Chung-Kuan Cheng, Xiaodong Yang, Walter H. Ku, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

An optimum placement search algorithm based on extended Corner Block List

Yici Cai, Jun Gu, Shuo Zhou, 2002, Journal of Computer Science and Technology.

An integrated floorplanning with an efficient buffer planning algorithm

Yici Cai, Jun Gu, Sheqin Dong, 2003, ISPD '03.

Optimal planning for mesh-based power distribution

Andrew B. Kahng, Chung-Kuan Cheng, Hongyu Chen, 2004 .

Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond

Chung-Kuan Cheng, Ilgweon Kang, 2017, ISPD.

Rectilinear block packing using O-tree representation

Chung-Kuan Cheng, Koen Lampaert, Yingxin Pang, 2001, ISPD '01.

Pin Redistribution for Multichip Module Designs

Chung-Kuan Cheng, Jae Dong Chung, Robert R. McBride, 1993 .

Empirical mode decomposition improves detection of SSVEP

Tzyy-Ping Jung, Yu-Te Wang, Yijun Wang, 2013, 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

New spectral linear placement and clustering approach

Chung-Kuan Cheng, Jianmin Li, Lung-Tien Liu, 1996, DAC '96.

Improved channel routing by via minimization and shifting

Chung-Kuan Cheng, David N. Deutsch, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

An Algorithmic Approach for Generic Parallel Adders

Jianhua Liu, Chung-Kuan Cheng, Haikun Zhu, 2003, ICCAD 2003.

A non-contact biopotential sensing system with motion artifact suppression

Chung-Kuan Cheng, Hui Wang, Hao Zhuang, 2013, 2013 International Conference on Communications, Circuits and Systems (ICCCAS).

High performance on-chip differential signaling using passive compensation for global communication

Masanori Hashimoto, Ling Zhang, Chung-Kuan Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

A fast time‐domain EM–TCAD coupled simulation framework via matrix exponential with stiffness reduction

Quan Chen, Ngai Wong, Chung-Kuan Cheng, 2016, Int. J. Circuit Theory Appl..

Empirical Study of Block Placement by Cluster Refinement

Jin Xu, Chung-Kuan Cheng, Pei-Ning Guo, 1999, VLSI Design.

Floorplanning with consideration of white space resource distribution for repeater planning

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, Sixth international symposium on quality electronic design (isqed'05).

A mulitple level network approach for clock skew minimization with process variations

Chung-Kuan Cheng, Bo Yao, Hongyu Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Exploring Cardioneural Signals from Noninvasive ECG Measurement

Yi Zhu, Chung-Kuan Cheng, Amirali Shayan Arani, 2007, 2007 IEEE 7th International Symposium on BioInformatics and BioEngineering.

A multi-chip module substrate testing algorithm

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

An experimental evaluation of partitioning algorithms

Chung-Kuan Cheng, T.-T.Y. Lin, Ching-Wei Yeh, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Application Multiple-Level Partitioning: An the Very Large-scale Hardware Simulator

Chung-Kuan Cheng, Yen-Chuen A. Wei, Yen-Chuen Wei, 1991 .

An algebraic multigrid solver for analytical placement with layout based clustering

Andrew B. Kahng, Chung-Kuan Cheng, Bo Yao, 2003, DAC '03.

Optimal wire sizing and buffer insertion for low power and a generalized delay model

Chung-Kuan Cheng, John Lillis, T.-T.Y. Lin, 1996 .

An Efficient Timing-Driven Global Routing Algorithm

Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh, 1993, 30th ACM/IEEE Design Automation Conference.

Arnoldi algorithms with structured orthogonalization

Chung-Kuan Cheng, Pengwen Chen, Xinyuan Wang, 2021, SIAM J. Numer. Anal..

CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation

Andrew B. Kahng, Chung-Kuan Cheng, Ilgweon Kang, 2021, 2021 IEEE 39th International Conference on Computer Design (ICCD).

Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT

Chung-Kuan Cheng, Bill Lin, Chia-Tung Ho, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs

Devon J. Merrill, Chung-Kuan Cheng, Ting-Chou Lin, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, 2021, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

GRA-LPO: Graph Convolution Based Leakage Power Optimization

Chung-Kuan Cheng, Uday Mallappa, Chung-Kuan Cheng, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC

Chung-Kuan Cheng, Bill Lin, Daeyeal Lee, 2021, IEEE Embedded Systems Letters.

Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning

Chung-Kuan Cheng, Bill Lin, Chester Holtz, 2021, 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes

Andrew B. Kahng, Hayoung Kim, Chung-Kuan Cheng, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interconnect analysis and synthesis. [Book Review]

Chung-Kuan Cheng, John Lillis, Stephen H Hall, 2001, IEEE Signal Processing Magazine.

CMOS Power Amplifiers for Wireless Communications

Peter M. Asbeck, Chung-Kuan Cheng, Lawrence E. Larson, 2003 .

VLSI floorplanning with boundary constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

The Y-architecture: yet another on-chip interconnect solution

Chung-Kuan Cheng, Bo Yao, Hongyu Chen, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

New spectral linear placement and clustering approach

Chung-Kuan Cheng, Lung-Tien Liu, John Lillis, 1996, 33rd Design Automation Conference Proceedings, 1996.

Symbolic analysis and reduction of VLSI circuits

Sheldon X.-D. Tan, Chung-Kuan Cheng, Zhanhai Qin, 2004 .

Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher, 2002 .

An Online Brain-Computer Interface Based on SSVEPs Measured From Non-Hair-Bearing Areas

Tzyy-Ping Jung, Chun-Shu Wei, Yijun Wang, 2017, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

Timing Optimization For Multi-source Nets: Characterization And Optimal Repeater Insertion

Chung-Kuan Cheng, J. Lillis, Chung-Kuan Cheng, 1997, Proceedings of the 34th Design Automation Conference.

Clock Skew Analysis via Vector Fitting in Frequency Domain

Wenjian Yu, Chung-Kuan Cheng, Haikun Zhu, 2008, ISQED 2008.

A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Satoshi Goto, Sheqin Dong, Chung-Kuan Cheng, 2008, ICCAD 2008.

Module placement with boundary constraints using O-tree representation

Yici Cai, Jun Gu, Sheqin Dong, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Floorplanning using a tree representation: a summary

Takeshi Yoshimura, Chung-Kuan Cheng, Pei-Ning Guo, 2003 .

Realizable parasitic reduction using generalized Y-/spl Delta/ transformation

Chung-Kuan Cheng, Zhanhai Qin, Chung-Kuan Cheng, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Dynamic analysis of power delivery network with nonlinear components using matrix exponential method

Chung-Kuan Cheng, Hao Zhuang, Ilgweon Kang, 2015, 2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity.

Estimation of Wirelength Reduction for λ-Geometry vs . Manhattan Placement and Routing

Chung-Kuan Cheng, Ion Mandoiu, Qinke Wang, 2003 .

The modular orientation of VLSI layout

Chung-Kuan Cheng, T. C. Hu, So-Zen Yao, 1990, IEEE International Symposium on Circuits and Systems.

Block placement with symmetry constraints based on the O-tree non-silicing representation

Chung-Kuan Cheng, K. Lampaert, Yingxin Pang, 2000, Proceedings 37th Design Automation Conference.

Fast post-placement rewiring using easily detectable functional symmetries

Chung-Kuan Cheng, M. Marek-Sadowska, P. Suaris, 2000, Proceedings 37th Design Automation Conference.

An efficient algorithm for the net matching problem

Masahiro Fujita, Chung-Kuan Cheng, Robert J. Carragher, 1993, ICCAD '93.

Algorithms for optimal introduction of redundant logic for timing and area optimization

Chung-Kuan Cheng, John Lillis, T.-T.Y. Lin, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.