Leibo Liu

发表

PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC

Chenchen Deng, Leibo Liu, Yang Liu, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Acceleration of control flows on Reconfigurable Architecture with a composite method

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Analog circuit optimization system based on hybrid evolutionary algorithms

Zheng Wang, Francisco V. Fernández, Yan Wang, 2009, Integr..

Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking

Yiyu Shi, Leibo Liu, Umamaheswara Rao Tida, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A VLSI architecture of JPEG2000 encoder

Hongyi Chen, Zhihua Wang, Leibo Liu, 2004 .

A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, IEICE Trans. Inf. Syst..

Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network

Dong Wang, Leibo Liu, Shouyi Yin, 2013, 2013 IEEE Eighth International Conference on Networking, Architecture and Storage.

A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT

Zhihua Wang, Hongyi Chen, Leibo Liu, 2002, Asia-Pacific Conference on Circuits and Systems.

Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation

Chunxiao Xing, Leibo Liu, Shouyi Yin, 2017, ACM Great Lakes Symposium on VLSI.

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications

Dong Wang, Chenchen Deng, Leibo Liu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

Duncan G. Elliott, Fabrizio Lombardi, Leibo Liu, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design and Implementation of an SD Interface to Multiple-Target Interface Bridge

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process

Chenchen Deng, Leibo Liu, Shouyi Yin, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An ASIC implementation of JPEG2000 codec

Zhihua Wang, Leibo Liu, Hongying Meng, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Reconfigurable Architecture for Neural Approximation in Multimedia Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Circuits and Systems for Video Technology.

Affine transformations for communication and reconfiguration optimization of loops on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

BriGuard: a lightweight indoor intrusion detection system based on infrared light spot displacement

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015 .

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Design and implementation of Reconfigurable Stream Processor in multimedia applications

Leibo Liu, Shaojun Wei, Yu Xiao, 2008, 2008 International Conference on Communications, Circuits and Systems.

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, FCCM 2014.

Outlook of Reconfigurable Cryptographic Processing Application Technology

Bo Wang, Leibo Liu, Shaojun Wei, 2018 .

Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parallelism optimization with variables affinity graph for reconfigurable computing architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, 2012 8th International Conference on Computing Technology and Information Management (NCM and ICNIT).

High-Performance Motion Estimation for Image Sensors with Video Compression

Zhiyong Liu, Leibo Liu, Shouyi Yin, 2015, Sensors.

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017, IEEE Transactions on Parallel and Distributed Systems.

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems

Terrence Mak, Xiaohang Wang, Ho-fung Leung, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits

Fabrizio Lombardi, Leibo Liu, Jie Han, 2017, ACM J. Emerg. Technol. Comput. Syst..

Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation

Leibo Liu, Jie Han, Xiaogang Song, 2018, IEEE Access.

A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, TRETS.

Energy-aware task partitioning and scheduling algorithm for reconfigurable processor

Rui Shi, Leibo Liu, Shouyi Yin, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

An interconnect interface for reconfigurable multimedia system

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).

Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Inf. Syst..

A VLSI design of sensor node for wireless image sensor network

Xinkai Chen, Leibo Liu, Shouyi Yin, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, Science China Information Sciences.

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only)

Lifeng Sun, Leibo Liu, Shouyi Yin, 2017, FPGA.

DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance

Chen Yang, Leibo Liu, Shouyi Yin, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Implementation of in-loop filter for HEVC decoder on reconfigurable processor

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017, IET Image Process..

An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform

Leibo Liu, Hongying Meng, Milin Zhang, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Inf. Syst..

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Parallel and Distributed Systems.

A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures

Fabrizio Lombardi, Leibo Liu, Jie Han, 2015, IEEE Transactions on Reliability.

Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Parallel and Distributed Systems.

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only)

Victor Y. Chen, Dong Wang, Leibo Liu, 2015, FPGA.

Prospect of the VLSI Architecture for Massive MIMO Detection

Leibo Liu, Shaojun Wei, Guiqiang Peng, 2019, Massive MIMO Detection Algorithm and VLSI Architecture.

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip

Longxing Shi, Leibo Liu, Shaojun Wei, 2013, IEICE Trans. Inf. Syst..

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Longxing Shi, Bo Liu, Leibo Liu, 2012, IEICE Trans. Inf. Syst..

A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems

Jianwei Cui, Leibo Liu, Shouyi Yin, 2011, 2011 9th IEEE International Conference on ASIC.

L-MPC: A LUT based MuIti-LeveI Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network

Qiang Li, Leibo Liu, Shaojun Wei, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, FPGA.

A VLSI architecture of EBCOT encoder for JPEG2000

Hongyi Chen, Zhihua Wang, Leibo Liu, 2003, ASICON 2003.

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, FPGA.

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Yu Peng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An automatic depth map generation for 2D-to-3D conversion

Zhen Zhang, Rui Shi, Hao Dong, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

A Hierarchical Local-Interconnection Structure for Reconfigurable Processing Unit

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration

Victor Y. Chen, Dong Wang, Leibo Liu, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

OPTMR: Optimal data flow graph partitioning for triple modular redundancy against hardware Trojan in reconfigurable hardware

Leibo Liu, Shengyang Mao, Leibo Liu, 2016, 2016 6th International Conference on Electronics Information and Emergency Communication (ICEIEC).

Trigger-Centric Loop Mapping on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Face Alignment With Expression- and Pose-Based Adaptive Initialization

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Multimedia.

Massive MIMO Detection Algorithm and VLSI Architecture

Leibo Liu, Shaojun Wei, Leibo Liu, 2019, Springer Singapore.

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamic priority assignment based task scheduling for battery-powered portable systems

Leibo Liu, Shaojun Wei, Yufeng Xie, 2007, 2007 7th International Conference on ASIC.

Reducing configuration contexts for coarse-grained reconfigurable architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Architecture of Linear Massive MIMO Detection

Leibo Liu, Shaojun Wei, Guiqiang Peng, 2019 .

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEICE Trans. Inf. Syst..

A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors

Fabrizio Lombardi, Leibo Liu, Jie Han, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Efficient Implementation of Advanced- Encryption-Standard Based on a Coarse-Grained Reconfigurable Processor

Le Chang, Leibo Liu, 2015 .

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

Xing Wang, Leibo Liu, Shouyi Yin, 2013, Science China Information Sciences.

Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, EMC/HumanCom.

A fast complete deblocking filter on a coarse-grained reconfigurable processor supporting H.264 high profile decoding

Zhihua Wang, Leibo Liu, Shouyi Yin, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shaojun Wei, Jianfeng Zhu, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints

Bruce F. Cockburn, Fabrizio Lombardi, Leibo Liu, 2019, ACM Great Lakes Symposium on VLSI.

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor

Guanyi Sun, Dong Wang, Leibo Liu, 2013, Science China Information Sciences.

An Efficient Kernel Transformation Architecture for Binary- and Ternary-Weight Neural Network Inference

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Compiler Framework for Reconfigurable Computing Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, IEICE Trans. Electron..

Minimizing pipeline stalls in distributed-controlled coarse-grained reconfigurable arrays with Triggered Instruction issue and execution

Jian Weng, Yangdong Deng, Chenchen Deng, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Automatic contexts switch in loop pipeline for embedded coarse-grained reconfigurable processor

Leibo Liu, Shaojun Wei, Sudong Yu, 2008, 2008 International Conference on Communications, Circuits and Systems.

Complex division and square-root using CORDIC

Dong Wang, Leibo Liu, Bohan Yang, 2012, 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet).

Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System

Hui Gao, Leibo Liu, Shouyi Yin, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature

Yike Guo, Leibo Liu, Shouyi Yin, 2015, Sensors.

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, Sensors.

A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines

Leibo Liu, Jie Han, Honglan Jiang, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution

Yangdong Deng, Leibo Liu, Shouyi Yin, 2018, IEEE Computer Architecture Letters.

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

H.264 parallel decoder at HD resolution on a coarse-grained reconfigurable multi-media system

Wenjie Wang, Leibo Liu, Shouyi Yin, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

A Novel Signed Truncated Booth Multiplier Based on Probability

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, CloudCom 2018.

Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture

Rui Shi, Leibo Liu, Shouyi Yin, 2015, IEICE Trans. Inf. Syst..

Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture

Rui Shi, Leibo Liu, Shouyi Yin, 2013, IEICE Trans. Inf. Syst..

Efficient memory partitioning for parallel data access in multidimensional arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 Symposium on VLSI Circuits.

Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture

Peng Zhang, Leibo Liu, Shouyi Yin, 2017, IEEE Transactions on Signal Processing.

Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Acceleration of nested conditionals on CGRAs via trigger scheme

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Access.

Battery aware tasks allocating algorithm for multi-battery operated system

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache

Yike Guo, Leibo Liu, Shouyi Yin, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Nonlinear Massive MIMO Signal Detection Algorithm

Leibo Liu, Shaojun Wei, Guiqiang Peng, 2019 .

Optimizing Spatial Mapping of Nested Loop for

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015 .

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA

Xiangyu Li, Leibo Liu, Shouyi Yin, 2018, DAC.

An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Journal of Solid-State Circuits.

A Stochastic Approach for the Analysis of Fault Trees With Priority AND Gates

Ming Jian Zuo, Leibo Liu, Jie Han, 2014, IEEE Transactions on Reliability.

Dynamically reconfigurable architecture for symmetric ciphers

Leibo Liu, Bo Wang, Bo D. Wang, 2016, Science China Information Sciences.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A fast and robust traffic sign recognition method using ring of RIBP histograms based feature

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Conference on Robotics and Biomimetics (ROBIO 2014).

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Circuits and Systems for Video Technology.

Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack

Hai Huang, Leibo Liu, Shouyi Yin, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Linear Massive MIMO Detection Algorithm

Leibo Liu, Shaojun Wei, Guiqiang Peng, 2019 .

Data compression and the 8×8 integer transform

Leibo Liu, Shaojun Wei, Min Zhu, 2009, 2009 IEEE 8th International Conference on ASIC.

A Reliable Physical Unclonable Function Based on Differential Charging Capacitors

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Approximate Arithmetic Circuits: Design and Evaluation

Fabrizio Lombardi, Leibo Liu, Jie Han, 2019, Approximate Circuits.

A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration

Yike Guo, Leibo Liu, Shouyi Yin, 2016, IEEE Computer Architecture Letters.

An efficient hardware design for cerebellar models using approximate circuits: special session paper

Leibo Liu, Jie Han, Honglan Jiang, 2017, CODES+ISSS.

A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power

Youyu Wu, Hui Li, Chenchen Deng, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC

Zhen Zhang, Leibo Liu, Shouyi Yin, 2012, IEICE Trans. Electron..

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

Victor Y. Chen, Li Zhou, Leibo Liu, 2013, Science China Information Sciences.

Area-efficient polynomial modular multiplication over GF(2∧n) and application to AES

Leibo Liu, Shaojun Wei, Hai Huang, 2017, 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN).

Gesture Recognition Approach on FPGA via Dynamic Time Warping

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012 .

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems

Sheng Zhou, Yang Xue, Leibo Liu, 2018, IEEE Transactions on Signal Processing.

An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices

Leibo Liu, Shouyi Yin, Wenping Zhu, 2014, IEEE Transactions on Consumer Electronics.

Efficient lane detection system based on monocular camera

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

A fast face detection architecture for auto-focus in smart-phones and digital cameras

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, Science China Information Sciences.

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT

Youguang Zhang, Leibo Liu, Shouyi Yin, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A new SAR DLL controller

Hongyi Chen, Leibo Liu, Lei Wang, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

CropNET: A Wireless Multimedia Sensor Network for Agricultural Monitoring

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, IEICE Trans. Commun..

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, J. Circuits Syst. Comput..

Joint Modulo Scheduling and $V_{\mathrm{ dd}}$ Assignment for Loop Mapping on Dual- $V_{\mathrm{ dd}}$ CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SPC: An Approach to Guarantee Performance in Cost Oriented Mapping Algorithm for NoC Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 IEEE Eighth International Conference on Networking, Architecture and Storage.

Real-time time-consistent 2D-to-3D video conversion based on color histogram

Zhen Zhang, Leibo Liu, Shouyi Yin, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

HCGM-based high-efficiency temperature evaluation scheme for NoCs

Leibo Liu, Chen Wu, Jiqiang Chen, 2016, 2016 6th International Conference on Electronics Information and Emergency Communication (ICEIEC).

Aggressive pipelining of irregular applications on reconfigurable hardware

Yao Wang, Yangdong Deng, Leibo Liu, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

A mapping algorithm for embedded coarse-grained reconfigurable processor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2008, 2008 International Conference on Communications, Circuits and Systems.

Scale Invariant Feature Transform algorithm based on a reconfigurable architecture system

Hui Gao, Leibo Liu, Shouyi Yin, 2012, 2012 8th International Conference on Computing Technology and Information Management (NCM and ICNIT).

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture

Chenchen Deng, Leibo Liu, Shouyi Yin, 2016, IEEE Transactions on Information Forensics and Security.

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Research on low-power neural network computing accelerator

Ying Zhang, Yuan Xie, Leibo Liu, 2019 .

Memory fartitioning-based modulo scheduling for high-level synthesis

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient and Flexible VLSI Architecture for Soft-Output Massive MIMO Detector

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, CloudCom 2018.

Examples of Reconfigurable Cryptographic Processor Design

Bo Wang, Leibo Liu, Shaojun Wei, 2018 .

User Behavior Pattern Analysis and Prediction Based on Mobile Phone Sensors

Leibo Liu, Jiqiang Song, Eugene Tang, 2010, NPC.

A high-throughput fixed-point complex divider for FPGAs

Dong Wang, Leibo Liu, Pengju Ren, 2013, IEICE Electron. Express.

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Bit-width Adaptive Accelerator Design for Convolution Neural Network

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

An automatic depth map generation method by image classification

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, J. Syst. Archit..

System level power modeling of reconfigurable processor using the least square method

Chenchen Deng, Leibo Liu, Shouyi Yin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

FP-BNN: Binarized neural network on FPGA

Wayne Luk, Leibo Liu, Shouyi Yin, 2018, Neurocomputing.

Multi-Battery Scheduling for Battery-Powered DVS Systems

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Commun..

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor

Long Wang, Victor Y. Chen, Dong Wang, 2013, Science China Information Sciences.

Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Constructing Concurrent Data Structures on FPGA with Channels

Hui Yan, Leibo Liu, Shouyi Yin, 2019, FPGA.

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, The 20th Asia and South Pacific Design Automation Conference.

A real-time time-consistent 2D-to-3D video conversion system using color histogram

Zhen Zhang, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Consumer Electronics.

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Inf. Syst..

A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Symposium on VLSI Circuits.

A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels

Xiao Yang, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A high performance parallel computing architecture for robust image features

Leibo Liu, Shaojun Wei, Renyan Zhou, 2014 .

Implementation of high throughput hardware efficient one-cycle cabac decoder

Xing Wang, Leibo Liu, Shouyi Yin, 2013 .

Performance evaluation modeling for reconfigurable processor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 9th IEEE International Conference on ASIC.

CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Polyhedral model based mapping optimization of loop nests for CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A novel hardware accelerator guideline for ANN with high performance

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Dynamic Reconfigurable Chips for Massive MIMO Detection

Leibo Liu, Shaojun Wei, Guiqiang Peng, 2019, Massive MIMO Detection Algorithm and VLSI Architecture.

Mapping deblocking algorithm of H.264 decoder onto a reconfigurable array architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).

A Full Multicast Reconfigurable Non-blocking Permutation Network

Hui Li, Leibo Liu, Shouyi Yin, 2018, 2018 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC).

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

Bo Wang, Chenchen Deng, Leibo Liu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A fast-locking and wide-range reversible SAR DLL

Hongyi Chen, Lei Wang, Leibo Liu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Compiler framework for reconfigurable computing system

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, 2009 International Conference on Communications, Circuits and Systems.

Optimizing buffer usage for Networks-on-Chip design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, 2009 International Conference on Communications, Circuits and Systems.

Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion

Zhen Zhang, Rui Shi, Hao Dong, 2017, IEEE Access.

RNA: A reconfigurable architecture for hardware neural acceleration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Neural approximating architecture targeting multiple application domains

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Analysis of the Reconfiguration Feature of Cryptographic Algorithms

Bo Wang, Leibo Liu, Shaojun Wei, 2018 .

A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing

Leibo Liu, Bo Wang, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Path-Changed Mirror Circuit against Local Electromagnetic Analysis

Bo Wang, Ao Li, Leibo Liu, 2018, 2018 13th APCA International Conference on Control and Soft Computing (CONTROLO).

Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Optimization of speeded-up robust feature algorithm for hardware implementation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, Science China Information Sciences.

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

VLSI design and implementation of the entropy decoder for multi-format video decoding algorithms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).

Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure

Chenchen Deng, Leibo Liu, Shouyi Yin, 2014, 2014 IEEE Frontiers in Education Conference (FIE) Proceedings.

DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach

Lifeng Sun, Leibo Liu, Shouyi Yin, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

Yu Peng, Leibo Liu, Shouyi Yin, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A high parallel motion compensation implementation on a coarse-grained reconfigurable processor supporting H.264 high profile decoding

Wei Liu, Leibo Liu, Shouyi Yin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Dong Wang, Leibo Liu, Shouyi Yin, 2016, IEICE Trans. Inf. Syst..

A novel application data coordinator for mobile computing systems

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Journal of Solid-State Circuits.

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

Temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

A reconfigurable multi-processor SoC for media applications

Wenjie Wang, Leibo Liu, Shouyi Yin, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

MapReduce inspired loop mapping for coarse-grained reconfigurable architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, Science China Information Sciences.

Multi-CNN and decision tree based driving behavior evaluation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, SAC.

Large-scale MIMO detection design and FPGA implementations using SOR method

Peng Zhang, Leibo Liu, Shaojun Wei, 2016, 2016 8th IEEE International Conference on Communication Software and Networks (ICCSN).

A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE Winter Conference on Applications of Computer Vision.

Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Design space exploration in multi-objective hierarchical SOC design

Leibo Liu, Shaojun Wei, Yufeng Xie, 2007, 2007 7th International Conference on ASIC.

Map-reduce inspired loop parallelization on CGRA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

Chao Yang, Leibo Liu, Shouyi Yin, 2009, 2009 IEEE 8th International Conference on ASIC.

Research on Anti-power Attack Technology Based on AES Improved Algorithm

Kai Luo, Leibo Liu, 2016 .

Hardware Architecture of Reconfigurable Cryptographic Processors

Bo Wang, Leibo Liu, Shaojun Wei, 2018 .

Fast and efficient integration of human upper-body detection and orientation estimation in RGB-D video

Leibo Liu, Shaojun Wei, Tao Ji, 2017, 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN).

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Dong Wang, Jun Yang, Leibo Liu, 2015, IEEE Transactions on Multimedia.

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, DAC.

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor

Victor Y. Chen, Dong Wang, Li Zhou, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, FPGA.

A new wireless sensor platform with camera

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011 .

An architecture of entropy decoder, inverse quantiser and predictor for multi-standard video decoding

Guanghui He, Leibo Liu, Shouyi Yin, 2014 .

Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

A parallel hardware architecture for fast integral image computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A graph covering method for template based system partition

Leibo Liu, Shaojun Wei, Muhua Han, 2008, 2008 International Conference on Communications, Circuits and Systems.

Low Bits: Binary Neural Network for Vad and Wakeup

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 5th International Conference on Information Science and Control Engineering (ICISCE).

Low-Power Reconfigurable Processor Utilizing Variable Dual $V_{\rm DD}$

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Energy management on DVS based coarse-grained reconfigurable platform

Chunxiao Xing, Leibo Liu, Shouyi Yin, 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

An Inductive-Coupling Interconnected Application-Specific 3D NoC Design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013 .

An inductive-coupling interconnected application-specific 3D NoC design

Zhen Zhang, Leibo Liu, Shouyi Yin, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Symposium on VLSI Circuits.

An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Systems Journal.

Adaptive approximation in arithmetic circuits: A low-power unsigned divider design

Fabrizio Lombardi, Leibo Liu, Jie Han, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

Xinkai Chen, Leibo Liu, Shouyi Yin, 2014 .

Multibank memory optimization for parallel data access in multiple data arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A FAST Extreme Illumination Robust Feature in Affine Space

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 22nd International Conference on Pattern Recognition.

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs

Yike Guo, Leibo Liu, Shouyi Yin, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A VLSI chip of SCLA based 2-D DWT/IDWT

Hongyi Chen, Zhihua Wang, Leibo Liu, 2003, ASICON 2003.

Battery-aware mapping optimization of loop nests for CGRAs

Yu Peng, Leibo Liu, Shouyi Yin, 2015, The 20th Asia and South Pacific Design Automation Conference.

Special session paper: an efficient hardware design for cerebellar models using approximate circuits

Leibo Liu, Jie Han, Honglan Jiang, 2017, 2017 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, Sensors.

A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching

Qiang Wang, Yiyu Shi, Leibo Liu, 2019, IEEE Transactions on Circuits and Systems for Video Technology.

A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing

Yuan Dong, Leibo Liu, Shouyi Yin, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Reconfigurable computing system: a project-based course for graduate students

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017 .

An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL

Hongyi Chen, Lei Wang, Leibo Liu, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 127 fps in full HD accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A 700fps optimized coarse-to-fine shape searching based hardware accelerator for face alignment

Qiang Wang, Chenchen Deng, Leibo Liu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints

Chenchen Deng, Leibo Liu, Shouyi Yin, 2014, Science China Information Sciences.

Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation

Fabrizio Lombardi, Leibo Liu, Jie Han, 2016, IEEE Transactions on Reliability.

Architecture for Nonlinear Massive MIMO Detection

Leibo Liu, Shaojun Wei, Guiqiang Peng, 2019 .

Battery-Aware Loop Nests Mapping for CGRAs

Yu Peng, Leibo Liu, Shouyi Yin, 2015, IEICE Trans. Inf. Syst..

Area-Efficient Delay-based PUF Based on Logic Gates

Bo Wang, Leibo Liu, Shaojun Wei, 2018, 2018 13th APCA International Conference on Control and Soft Computing (CONTROLO).

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding"

Dong Wang, Jun Yang, Leibo Liu, 2015, IEEE Trans. Multim..

Low-Power Low-Cost Implementation of IEEE 802.15.4 in WiSN SoC Design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 6th International Conference on Wireless Communications Networking and Mobile Computing (WiCOM).

A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, Sensors.

Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications

Yang Zhang, Bo Liu, Leibo Liu, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays

Yiyu Shi, Yangdong Deng, Leibo Liu, 2018, IEEE Transactions on Parallel and Distributed Systems.

REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only)

Leibo Liu, Bo Wang, 2015, FPGA.

Physical Attack Countermeasures for Reconfigurable Cryptographic Processors

Bo Wang, Leibo Liu, Shaojun Wei, 2018 .

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

VLSI architecture of EBCOT Tier-2 encoder for JPEG2000

Li Zhang, Ning Chen, Leibo Liu, 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

Hardware efficient signal detector based on lanczos method for massive MIMO systems

Yang Xue, Leibo Liu, Shouyi Yin, 2017, 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN).

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, IEICE Trans. Inf. Syst..

Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Parallel and Distributed Systems.

LCP: a Layer Clusters Paralleling mapping method for accelerating Inception and Residual networks on FPGA

Xiangyu Li, Leibo Liu, Shouyi Yin, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Design methodology of low power JPEG2000 codec exploiting dual voltage scaling

Li Zhang, Leibo Liu, Zhihua Wang, 2005, 2005 6th International Conference on ASIC.

Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor Platforms

Rui Dai, Leibo Liu, Shaojun Wei, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Mixed-level modeling for network on chip infrastructure in SoC design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.