Shouyi Yin

发表

PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC

Chenchen Deng, Leibo Liu, Yang Liu, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Acceleration of control flows on Reconfigurable Architecture with a composite method

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

24.4 Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation

Jun Yang, Yan Liu, Shouyi Yin, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, IEICE Trans. Inf. Syst..

Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network

Dong Wang, Leibo Liu, Shouyi Yin, 2013, 2013 IEEE Eighth International Conference on Networking, Architecture and Storage.

Testbench generation for reconfigurable media processor

Shouyi Yin, Shaojun Wei, Chenyang Wang, 2008, 2008 International Conference on Communications, Circuits and Systems.

Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation

Chunxiao Xing, Leibo Liu, Shouyi Yin, 2017, ACM Great Lakes Symposium on VLSI.

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications

Dong Wang, Chenchen Deng, Leibo Liu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Design and Implementation of an SD Interface to Multiple-Target Interface Bridge

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process

Chenchen Deng, Leibo Liu, Shouyi Yin, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reconfigurable Architecture for Neural Approximation in Multimedia Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Circuits and Systems for Video Technology.

Affine transformations for communication and reconfiguration optimization of loops on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

BriGuard: a lightweight indoor intrusion detection system based on infrared light spot displacement

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015 .

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Traffic-aware routing for real-time communications in wireless multi-hop networks: Research Articles

Xiaokang Lin, Shouyi Yin, Yongqiang Xiong, 2006 .

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, FCCM 2014.

Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parallelism optimization with variables affinity graph for reconfigurable computing architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, 2012 8th International Conference on Computing Technology and Information Management (NCM and ICNIT).

High-Performance Motion Estimation for Image Sensors with Video Compression

Zhiyong Liu, Leibo Liu, Shouyi Yin, 2015, Sensors.

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017, IEEE Transactions on Parallel and Distributed Systems.

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems

Terrence Mak, Xiaohang Wang, Ho-fung Leung, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, TRETS.

Energy-aware task partitioning and scheduling algorithm for reconfigurable processor

Rui Shi, Leibo Liu, Shouyi Yin, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

An interconnect interface for reconfigurable multimedia system

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).

Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Inf. Syst..

A VLSI design of sensor node for wireless image sensor network

Xinkai Chen, Leibo Liu, Shouyi Yin, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, Science China Information Sciences.

GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent

Yangdong Deng, Shouyi Yin, Yifan Yang, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only)

Lifeng Sun, Leibo Liu, Shouyi Yin, 2017, FPGA.

DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance

Chen Yang, Leibo Liu, Shouyi Yin, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Implementation of in-loop filter for HEVC decoder on reconfigurable processor

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017, IET Image Process..

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture

Zhiwei Liu, Shouyi Yin, Zhaoshi Li, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory

Yangdong Deng, Shouyi Yin, Jiawei Wang, 2019, MICRO.

Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT

Chen Chen, Shouyi Yin, Bohan Yang, 2020 .

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Inf. Syst..

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Parallel and Distributed Systems.

Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation

Shouyi Yin, Shaojun Wei, Jianfeng Zhu, 2020, IEEE Transactions on Parallel and Distributed Systems.

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Parallel and Distributed Systems.

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only)

Victor Y. Chen, Dong Wang, Leibo Liu, 2015, FPGA.

A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs

Shouyi Yin, Ning Li, Shaojun Wei, 2020, 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction

Yang Wang, Shouyi Yin, Feng Xiong, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems

Jianwei Cui, Leibo Liu, Shouyi Yin, 2011, 2011 9th IEEE International Conference on ASIC.

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, FPGA.

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, FPGA.

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Yu Peng, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An automatic depth map generation for 2D-to-3D conversion

Zhen Zhang, Rui Shi, Hao Dong, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

A Hierarchical Local-Interconnection Structure for Reconfigurable Processing Unit

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration

Victor Y. Chen, Dong Wang, Leibo Liu, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions

Chenchen Deng, Shouyi Yin, Junbin Wang, 2016, IEEE Transactions on Parallel and Distributed Systems.

Trigger-Centric Loop Mapping on CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs

Xiaohang Wang, Shouyi Yin, Liang Wang, 2020 .

Face Alignment With Expression- and Pose-Based Adaptive Initialization

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Multimedia.

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reducing configuration contexts for coarse-grained reconfigurable architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision

George Jie Yuan, Shouyi Yin, Shaojun Wei, 2014, IEEE Journal of Solid-State Circuits.

A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network

Shouyi Yin, Shaojun Wei, Weisheng Zhao, 2019, ACM Great Lakes Symposium on VLSI.

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEICE Trans. Inf. Syst..

Traffic-aware Routing for RTC in Wireless Multi-hop Networks

Xiaokang Lin, Shouyi Yin, Yongqiang Xiong, 2007 .

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

Xing Wang, Leibo Liu, Shouyi Yin, 2013, Science China Information Sciences.

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory

Cong Xu, Yuan Xie, Jishen Zhao, 2019, IEEE Transactions on Parallel and Distributed Systems.

Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, EMC/HumanCom.

A fast complete deblocking filter on a coarse-grained reconfigurable processor supporting H.264 high profile decoding

Zhihua Wang, Leibo Liu, Shouyi Yin, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor

Guanyi Sun, Dong Wang, Leibo Liu, 2013, Science China Information Sciences.

An Efficient Kernel Transformation Architecture for Binary- and Ternary-Weight Neural Network Inference

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Compiler Framework for Reconfigurable Computing Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, IEICE Trans. Electron..

Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System

Hui Gao, Leibo Liu, Shouyi Yin, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality

Nanning Zheng, Xiang Li, Hongbin Sun, 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature

Yike Guo, Leibo Liu, Shouyi Yin, 2015, Sensors.

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings

Xiaohang Wang, Shouyi Yin, Liang Wang, 2020, IEEE Transactions on Parallel and Distributed Systems.

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, Sensors.

A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Traffic-aware routing for real time communications in wireless multi-hop networks

Qian Zhang, Xiaokang Lin, Shouyi Yin, 2006, IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC'06).

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution

Yangdong Deng, Leibo Liu, Shouyi Yin, 2018, IEEE Computer Architecture Letters.

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

H.264 parallel decoder at HD resolution on a coarse-grained reconfigurable multi-media system

Wenjie Wang, Leibo Liu, Shouyi Yin, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

A Novel Signed Truncated Booth Multiplier Based on Probability

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, CloudCom 2018.

Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS

Xi Chen, Meng-Fan Chang, Shouyi Yin, 2019, 2019 Symposium on VLSI Circuits.

A Fast and Low Power Hardware Accelerator for ANN Working at Near Threshold Voltage

Shouyi Yin, Shaojun Wei, Tianbao Chen, 2016 .

Prediction-based routing for real time communications in wireless multi-hop networks

Qian Zhang, Xiaokang Lin, Shouyi Yin, 2006, QShine '06.

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture

Rui Shi, Leibo Liu, Shouyi Yin, 2015, IEICE Trans. Inf. Syst..

Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture

Rui Shi, Leibo Liu, Shouyi Yin, 2013, IEICE Trans. Inf. Syst..

Efficient memory partitioning for parallel data access in multidimensional arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 Symposium on VLSI Circuits.

Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture

Peng Zhang, Leibo Liu, Shouyi Yin, 2017, IEEE Transactions on Signal Processing.

A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network

Youguang Zhang, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Magnetics.

Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Acceleration of nested conditionals on CGRAs via trigger scheme

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Access.

Battery aware tasks allocating algorithm for multi-battery operated system

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache

Yike Guo, Leibo Liu, Shouyi Yin, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

THUEE System for NIST SRE19 CTS Challenge

Shouyi Yin, Xianwei Zhang, Xianhong Chen, 2020, INTERSPEECH.

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Yangdong Deng, Shouyi Yin, Jianfeng Zhu, 2019, ACM Comput. Surv..

Optimizing Spatial Mapping of Nested Loop for

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015 .

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA

Xiangyu Li, Leibo Liu, Shouyi Yin, 2018, DAC.

An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Journal of Solid-State Circuits.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A fast and robust traffic sign recognition method using ring of RIBP histograms based feature

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Conference on Robotics and Biomimetics (ROBIO 2014).

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Circuits and Systems for Video Technology.

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA

Shouyi Yin, Hailong Yao, Shaojun Wei, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack

Hai Huang, Leibo Liu, Shouyi Yin, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Reliable Physical Unclonable Function Based on Differential Charging Capacitors

Leibo Liu, Shouyi Yin, Shaojun Wei, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration

Yike Guo, Leibo Liu, Shouyi Yin, 2016, IEEE Computer Architecture Letters.

A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power

Youyu Wu, Hui Li, Chenchen Deng, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC

Zhen Zhang, Leibo Liu, Shouyi Yin, 2012, IEICE Trans. Electron..

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

Victor Y. Chen, Li Zhou, Leibo Liu, 2013, Science China Information Sciences.

A 1096fps Hardware Architecture for Fast Training in Object Tracking

Shouyi Yin, Qiang Li, Shaojun Wei, 2019, 2019 IEEE 11th International Conference on Communication Software and Networks (ICCSN).

Gesture Recognition Approach on FPGA via Dynamic Time Warping

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012 .

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems

Sheng Zhou, Yang Xue, Leibo Liu, 2018, IEEE Transactions on Signal Processing.

Performance Comparison of Multipath Routing Algorithms for TCP Traffic

Xiaokang Lin, Guangyi Liu, Shouyi Yin, 2003 .

Transformer with Bidirectional Decoder for Speech Recognition

Shouyi Yin, Xi Chen, Songyang Zhang, 2020, INTERSPEECH.

Xiaokang Lin, Shouyi Yin, 2005, Second IFIP International Conference on Wireless and Optical Communications Networks, 2005. WOCN 2005..

An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices

Leibo Liu, Shouyi Yin, Wenping Zhu, 2014, IEEE Transactions on Consumer Electronics.

Efficient lane detection system based on monocular camera

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

A fast face detection architecture for auto-focus in smart-phones and digital cameras

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, Science China Information Sciences.

A general configurable wireless sensor network system based on SD card

Hui Gao, Shouyi Yin, Shaojun Wei, 2012, 2012 8th International Conference on Computing Technology and Information Management (NCM and ICNIT).

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT

Youguang Zhang, Leibo Liu, Shouyi Yin, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions

Shouyi Yin, Weiwei Wu, Fengbin Tu, 2019, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS).

CropNET: A Wireless Multimedia Sensor Network for Agricultural Monitoring

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, IEICE Trans. Commun..

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, J. Circuits Syst. Comput..

Joint Modulo Scheduling and $V_{\mathrm{ dd}}$ Assignment for Loop Mapping on Dual- $V_{\mathrm{ dd}}$ CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SPC: An Approach to Guarantee Performance in Cost Oriented Mapping Algorithm for NoC Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 IEEE Eighth International Conference on Networking, Architecture and Storage.

Real-time time-consistent 2D-to-3D video conversion based on color histogram

Zhen Zhang, Leibo Liu, Shouyi Yin, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

THUEE system description for NIST 2019 SRE CTS Challenge pdf

Shouyi Yin, Xianwei Zhang, Xianhong Chen, 2019, ArXiv.

Aggressive pipelining of irregular applications on reconfigurable hardware

Yao Wang, Yangdong Deng, Leibo Liu, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

A fast and power efficient architecture to parallelize LSTM based RNN for cognitive intelligence applications

Shouyi Yin, Shaojun Wei, Peng Ouyang, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Reconfigurable Branch Predictor for Spatial Computing Architectures

Shouyi Yin, Jian Liu, Yanan Lu, 2020, ICDSP.

A mapping algorithm for embedded coarse-grained reconfigurable processor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2008, 2008 International Conference on Communications, Circuits and Systems.

Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning

Yang Wang, Shouyi Yin, Ning Li, 2021, IEEE Journal of Solid-State Circuits.

Scale Invariant Feature Transform algorithm based on a reconfigurable architecture system

Hui Gao, Leibo Liu, Shouyi Yin, 2012, 2012 8th International Conference on Computing Technology and Information Management (NCM and ICNIT).

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture

Chenchen Deng, Leibo Liu, Shouyi Yin, 2016, IEEE Transactions on Information Forensics and Security.

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Research on low-power neural network computing accelerator

Ying Zhang, Yuan Xie, Leibo Liu, 2019 .

Multipath minimum energy routing in ad hoc network

Xiaokang Lin, Shouyi Yin, Xiaokang Lin, 2005, IEEE International Conference on Communications, 2005. ICC 2005. 2005.

Memory fartitioning-based modulo scheduling for high-level synthesis

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient and Flexible VLSI Architecture for Soft-Output Massive MIMO Detector

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, CloudCom 2018.

MSAM: A Multi-Layer Bi-LSTM Based Speech to Vector Model with Residual Attention Mechanism

Shouyi Yin, Dongdong Cui, Shaojun Wei, 2019, 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Efficient Scheduling of Irregular Network Structures on CNN Accelerators

Shouyi Yin, Shibin Tang, Shaojun Wei, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Bit-width Adaptive Accelerator Design for Convolution Neural Network

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

An automatic depth map generation method by image classification

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, J. Syst. Archit..

System level power modeling of reconfigurable processor using the least square method

Chenchen Deng, Leibo Liu, Shouyi Yin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

FP-BNN: Binarized neural network on FPGA

Wayne Luk, Leibo Liu, Shouyi Yin, 2018, Neurocomputing.

Multi-Battery Scheduling for Battery-Powered DVS Systems

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Commun..

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor

Long Wang, Victor Y. Chen, Dong Wang, 2013, Science China Information Sciences.

Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks

Bo Wang, Chenchen Deng, Shouyi Yin, 2017, IEEE Transactions on Information Forensics and Security.

Constructing Concurrent Data Structures on FPGA with Channels

Hui Yan, Leibo Liu, Shouyi Yin, 2019, FPGA.

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures

Chenchen Deng, Leibo Liu, Shouyi Yin, 2015, The 20th Asia and South Pacific Design Automation Conference.

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration

Shouyi Yin, Shaojun Wei, Jiangyuan Gu, 2018, IEEE Transactions on Parallel and Distributed Systems.

A real-time time-consistent 2D-to-3D video conversion system using color histogram

Zhen Zhang, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Consumer Electronics.

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2012, IEICE Trans. Inf. Syst..

PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement

Shouyi Yin, Peng Ouyang, Zihang Jiang, 2020, ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Symposium on VLSI Circuits.

A template mapping algorithm for reconfigurable computing

Shouyi Yin, Shaojun Wei, Yansheng Wang, 2008, 2008 International Conference on Communications, Circuits and Systems.

An STT-MRAM Based in Memory Architecture for Low Power Integral Computing

Youguang Zhang, Shouyi Yin, Shaojun Wei, 2019, IEEE Transactions on Computers.

Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation

Shouyi Yin, Pan Wang, Sheng Zhou, 2020, IEEE Transactions on Wireless Communications.

A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels

Xiao Yang, Leibo Liu, Shouyi Yin, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Implementation of high throughput hardware efficient one-cycle cabac decoder

Xing Wang, Leibo Liu, Shouyi Yin, 2013 .

MALB: MANET adaptive load balancing

Xiaokang Lin, Shouyi Yin, Xiaokang Lin, 2004, IEEE 60th Vehicular Technology Conference, 2004. VTC2004-Fall. 2004.

Performance evaluation modeling for reconfigurable processor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 9th IEEE International Conference on ASIC.

CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Polyhedral model based mapping optimization of loop nests for CGRAs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A novel hardware accelerator guideline for ANN with high performance

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Mapping deblocking algorithm of H.264 decoder onto a reconfigurable array architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).

A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection

Shouyi Yin, Sheng Zhou, Shaojun Wei, 2020, IEEE Journal of Solid-State Circuits.

A Full Multicast Reconfigurable Non-blocking Permutation Network

Hui Li, Leibo Liu, Shouyi Yin, 2018, 2018 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC).

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

Bo Wang, Chenchen Deng, Leibo Liu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Compiler framework for reconfigurable computing system

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, 2009 International Conference on Communications, Circuits and Systems.

Optimizing buffer usage for Networks-on-Chip design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, 2009 International Conference on Communications, Circuits and Systems.

Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion

Zhen Zhang, Rui Shi, Hao Dong, 2017, IEEE Access.

RNA: A reconfigurable architecture for hardware neural acceleration

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT

Chen Chen, Shouyi Yin, Shaojun Wei, 2020, IACR Trans. Cryptogr. Hardw. Embed. Syst..

Neural approximating architecture targeting multiple application domains

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform

Shouyi Yin, Cong Liu, Yang Hu, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A parallel implementation of MP3 decoding algorithm on Reconfigurable Computing systems

Shouyi Yin, Shaojun Wei, Chongyong Yin, 2008, 2008 International Conference on Communications, Circuits and Systems.

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Traffic scheduling for application specific Networks-on-Chip

Shouyi Yin, 2008, 2008 International Conference on Communications, Circuits and Systems.

Optimization of speeded-up robust feature algorithm for hardware implementation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, Science China Information Sciences.

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

VLSI design and implementation of the entropy decoder for multi-format video decoding algorithms

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet).

Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure

Chenchen Deng, Leibo Liu, Shouyi Yin, 2014, 2014 IEEE Frontiers in Education Conference (FIE) Proceedings.

DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach

Lifeng Sun, Leibo Liu, Shouyi Yin, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

Yu Peng, Leibo Liu, Shouyi Yin, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A high parallel motion compensation implementation on a coarse-grained reconfigurable processor supporting H.264 high profile decoding

Wei Liu, Leibo Liu, Shouyi Yin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Multipath Energy Efficient Routing in Mobile Ad Hoc Network

Xiaokang Lin, Shouyi Yin, 2005, ICN.

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Dong Wang, Leibo Liu, Shouyi Yin, 2016, IEICE Trans. Inf. Syst..

A novel application data coordinator for mobile computing systems

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, IEEE Journal of Solid-State Circuits.

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

A Multi-Task Hardwired Accelerator for Face Detection and Alignment

Hong Liu, Shouyi Yin, Qiang Li, 2020, IEEE Transactions on Circuits and Systems for Video Technology.

Temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

A reconfigurable multi-processor SoC for media applications

Wenjie Wang, Leibo Liu, Shouyi Yin, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Addition Circuit optimization Using Carry-Lookahead and SIMD for Homomorphic Encryption

Shouyi Yin, Shaojun Wei, Leibo Liu, 2019, 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

MapReduce inspired loop mapping for coarse-grained reconfigurable architecture

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, Science China Information Sciences.

Multi-CNN and decision tree based driving behavior evaluation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, SAC.

A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 IEEE Winter Conference on Applications of Computer Vision.

An On-Chip Interconnect Mechanism for Multi-processor SoC

Shouyi Yin, Shaojun Wei, Jiyao Liu, 2012 .

A 4K $\times$ 2K@60fps Multifunctional Video Display Processor for High Perceptual Image Quality

Nanning Zheng, Hongbin Sun, Shouyi Yin, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A High Precision Feature Based on LBP and Gabor Theory for Face Recognition

Shouyi Yin, Wei Xia, Peng Ouyang, 2013, Sensors.

Map-reduce inspired loop parallelization on CGRA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient Comparison and Addition for FHE with Weighted Computational Complexity Model

Shouyi Yin, Bohan Yang, Shaojun Wei, 2020 .

A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

Chao Yang, Leibo Liu, Shouyi Yin, 2009, 2009 IEEE 8th International Conference on ASIC.

Architecture, challenges and applications of dynamic reconfigurable computing

Shouyi Yin, Yanan Lu, Shaojun Wei, 2020, Journal of Semiconductors.

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Dong Wang, Jun Yang, Leibo Liu, 2015, IEEE Transactions on Multimedia.

Towards Efficient Compact Network Training on Edge-Devices

Shouyi Yin, Fengbin Tu, Shaojun Wei, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, DAC.

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor

Victor Y. Chen, Dong Wang, Li Zhou, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Traffic-aware routing for real-time communications in wireless multi-hop networks

Qian Zhang, Xiaokang Lin, Shouyi Yin, 2006, Wirel. Commun. Mob. Comput..

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, FPGA.

A new wireless sensor platform with camera

Leibo Liu, Shouyi Yin, Shaojun Wei, 2011 .

Small-Footprint Keyword Spotting with Graph Convolutional Network

Shouyi Yin, Xi Chen, Peng Ouyang, 2019, 2019 IEEE Automatic Speech Recognition and Understanding Workshop (ASRU).

An architecture of entropy decoder, inverse quantiser and predictor for multi-standard video decoding

Guanghui He, Leibo Liu, Shouyi Yin, 2014 .

Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

A parallel hardware architecture for fast integral image computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks

Shouyi Yin, Shaojun Wei, Leibo Liu, 2019, 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms

Kai Lu, Shouyi Yin, Jiawei Wang, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Low Bits: Binary Neural Network for Vad and Wakeup

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 5th International Conference on Information Science and Control Engineering (ICISCE).

FPGA Accelerated DAN Algorithm with Weight Decomposition for Face Alignment

Qiang Li, Shouyi Yin, Lu Zhan, 2019, 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Low-Power Reconfigurable Processor Utilizing Variable Dual $V_{\rm DD}$

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Energy management on DVS based coarse-grained reconfigurable platform

Chunxiao Xing, Leibo Liu, Shouyi Yin, 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014 .

An Inductive-Coupling Interconnected Application-Specific 3D NoC Design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2013 .

An inductive-coupling interconnected application-specific 3D NoC design

Zhen Zhang, Leibo Liu, Shouyi Yin, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Efficient Hardware Architecture of Softmax Layer in Deep Neural Network

Shouyi Yin, Shaojun Wei, Binren Tian, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Symposium on VLSI Circuits.

An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation

Leibo Liu, Shouyi Yin, Shaojun Wei, 2017, IEEE Systems Journal.

An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning

Shouyi Yin, Dandan Song, Peng Ouyang, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

Xinkai Chen, Leibo Liu, Shouyi Yin, 2014 .

Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor

Yong Wang, Shouyi Yin, Ao Luo, 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication

Shouyi Yin, Leibo Liu, Neng Zhang, 2020, IEEE Transactions on Computers.

Multibank memory optimization for parallel data access in multiple data arrays

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A FAST Extreme Illumination Robust Feature in Affine Space

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 22nd International Conference on Pattern Recognition.

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs

Yike Guo, Leibo Liu, Shouyi Yin, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Battery-aware mapping optimization of loop nests for CGRAs

Yu Peng, Leibo Liu, Shouyi Yin, 2015, The 20th Asia and South Pacific Design Automation Conference.

Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation

Shouyi Yin, Shaojun Wei, Binren Tian, 2018, J. Low Power Electron..

A portable environmental monitoring system based on WSN for off-the-shelf sensors

Hui Gao, Shouyi Yin, Shaojun Wei, 2011, 2011 International Conference on Computational Problem-Solving (ICCP).

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps

Leibo Liu, Shouyi Yin, Shaojun Wei, 2014, Sensors.

A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching

Qiang Wang, Yiyu Shi, Leibo Liu, 2019, IEEE Transactions on Circuits and Systems for Video Technology.

A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing

Yuan Dong, Leibo Liu, Shouyi Yin, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Reconfigurable computing system: a project-based course for graduate students

Chenchen Deng, Leibo Liu, Shouyi Yin, 2017 .

A 127 fps in full HD accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints

Chenchen Deng, Leibo Liu, Shouyi Yin, 2014, Science China Information Sciences.

Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems

Shouyi Yin, Sheng Zhou, Shaojun Wei, 2020, IEEE Transactions on Signal Processing.

Battery-Aware Loop Nests Mapping for CGRAs

Yu Peng, Leibo Liu, Shouyi Yin, 2015, IEICE Trans. Inf. Syst..

A Computing Efficient Hardware Architecture for Sparse Deep Neural Network Computing

Youguang Zhang, Shouyi Yin, Shaojun Wei, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding"

Dong Wang, Jun Yang, Leibo Liu, 2015, IEEE Trans. Multim..

Fast and low-power behavior analysis on vehicles using smartphones

Shouyi Yin, Peng Ouyang, Xiaoqing Xu, 2017, 2017 6th International Symposium on Next Generation Electronics (ISNE).

Low-Power Low-Cost Implementation of IEEE 802.15.4 in WiSN SoC Design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 6th International Conference on Wireless Communications Networking and Mobile Computing (WiCOM).

A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems

Leibo Liu, Shouyi Yin, Shaojun Wei, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps

Leibo Liu, Shouyi Yin, Shaojun Wei, 2015, Sensors.

Adaptive load balancing in mobile ad hoc networks

Xiaokang Lin, Shouyi Yin, Xiaokang Lin, 2005, IEEE Wireless Communications and Networking Conference, 2005.

Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays

Yiyu Shi, Yangdong Deng, Leibo Liu, 2018, IEEE Transactions on Parallel and Distributed Systems.

Stress-aware loops mapping on CGRAs with considering NBTI aging effect

Shouyi Yin, Shaojun Wei, Jiangyuan Gu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hardware efficient signal detector based on lanczos method for massive MIMO systems

Yang Xue, Leibo Liu, Shouyi Yin, 2017, 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN).

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, IEICE Trans. Inf. Syst..

Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures

Leibo Liu, Shouyi Yin, Shaojun Wei, 2016, IEEE Transactions on Parallel and Distributed Systems.

LCP: a Layer Clusters Paralleling mapping method for accelerating Inception and Residual networks on FPGA

Xiangyu Li, Leibo Liu, Shouyi Yin, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks

Shouyi Yin, Ang Li, Wenjing Hu, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Mixed-level modeling for network on chip infrastructure in SoC design

Leibo Liu, Shouyi Yin, Shaojun Wei, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization

Xin Si, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

Shouyi Yin, Yuyao Kong, Leibo Liu, 2021, IEEE Journal of Solid-State Circuits.

Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs

Shouyi Yin, Jiaxing Shang, Dajiang Liu, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning

Yang Wang, Shouyi Yin, Fengbin Tu, 2021, IEEE Journal of Solid-State Circuits.

A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation

Shouyi Yin, Ruiqi Guo, Zhixiao Zhang, 2021, 2021 Symposium on VLSI Circuits.

ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training

Shouyi Yin, Xinhan Lin, Fengbin Tu, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction

Shouyi Yin, Leibo Liu, Huiyu Mo, 2021, IEEE Journal of Solid-State Circuits.

Dynamic-II Pipeline: Compiling Loops with Irregular Branches on Static-Scheduling CGRA

Shouyi Yin, Jianfeng Zhu, Leibo Liu, 2021 .

Flexible Rectification of a Speckle Projection System for Depth Sensing

Shouyi Yin, Shibin Tang, Peng Ouyang, 2021, IEEE Transactions on Instrumentation and Measurement.

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Shouyi Yin, Leibo Liu, Shaojun Wei, 2021, IACR Trans. Cryptogr. Hardw. Embed. Syst..

An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures

Yangdong Deng, Shouyi Yin, Xiaowei Jiang, 2021, IEEE Transactions on Parallel and Distributed Systems.

A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding

Shouyi Yin, Leibo Liu, Neng Zhang, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium

Shouyi Yin, Zhengdong Li, Leibo Liu, 2021, IACR Trans. Cryptogr. Hardw. Embed. Syst..

Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters

Yong Wang, Chenchen Deng, Shouyi Yin, 2021, IEEE Journal of Solid-State Circuits.

Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning

Yang Wang, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms

Shouyi Yin, Leibo Liu, Shaojun Wei, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast

Shouyi Yin, Shaojun Wei, Leibo Liu, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

LPE: Logarithm Posit Processing Element for Energy-Efficient Edge-Device Training

Yang Wang, Shouyi Yin, Shaojun Wei, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption

Shouyi Yin, Xulong Tang, Zihang Jiang, 2021, 2021 IEEE 30th Asian Test Symposium (ATS).

A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation

Yang Wang, Shouyi Yin, Xinhan Lin, 2021, 2021 Symposium on VLSI Circuits.

An ultra-high energy-efficient reconfigurable processor for deep neural networks with binary / ternary weights in 28 nm CMOS

Shouyi Yin, Shaojun Wei, Peng Ouyang, 2018 .

HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing

Chen Yang, Chenchen Deng, Shouyi Yin, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video

Shouyi Yin, Shaojun Wei, Weilong Zhang, 2013, Science China Information Sciences.

A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS

Shouyi Yin, Shaojun Wei, Leibo Liu, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Disturbance aware memory partitioning for parallel data access in STT-RAM

Shouyi Yin, Shaojun Wei, Zhicong Xie, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).