ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY
暂无分享,去创建一个
[1] Abhijit Chatterjee,et al. Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level , 2003, ICCAD 2003.
[2] N. Bansal,et al. Analysis of the Performance of Coarse-Grain Reconfigurable Architectures with Different Processing Element Configurations , 2003 .
[3] Russell Tessier,et al. ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).
[4] S. Natarajan,et al. Searching for the dream embedded memory , 2009, IEEE Solid-State Circuits Magazine.
[5] Carl Ebeling,et al. Architecture design of reconfigurable pipelined datapaths , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.
[6] L. Litwin,et al. Error control coding , 2001 .
[7] Kinam Kim,et al. Memory Technologies for sub-40nm Node , 2007, 2007 IEEE International Electron Devices Meeting.
[8] André DeHon,et al. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[9] Carl Ebeling,et al. Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays , 2009, 2009 International Conference on Field Programmable Logic and Applications.
[10] David Haccoun,et al. Adaptive Viterbi decoding of convolutional codes over memoryless channels , 1997, IEEE Trans. Commun..
[11] Seth Copen Goldstein,et al. PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.
[12] Cao Liang,et al. SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications , 2009, EURASIP J. Embed. Syst..
[13] Dennis Goeckel,et al. An adaptive Reed-Solomon errors-and-erasures decoder , 2006, FPGA '06.
[14] Scott A. Mahlke,et al. Bridging the computation gap between programmable processors and hardwired accelerators , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.
[15] Vladimir A. Labay,et al. Reed-Solomon Error Correction , 2015 .
[16] Nanning Zheng,et al. Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[17] Dirk Grunwald,et al. Pipeline gating: speculation control for energy reduction , 1998, ISCA.
[18] Mircea R. Stan,et al. The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory , 2010, Proceedings of the IEEE.
[19] Rudy Lauwereins,et al. Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.
[20] Anthony J. Yu,et al. Directional and single-driver wires in FPGA interconnect , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).
[21] George Theodoridis,et al. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools , 2007 .
[22] ZhangTong,et al. Exploring the use of emerging nonvolatile memory technologies in future FPGAs , 2013 .
[23] Stanley J. Simmons,et al. Breadth-first trellis decoding with adaptive effort , 1990, IEEE Trans. Commun..
[24] Yiran Chen,et al. Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM) , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[25] Carl Ebeling,et al. RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.
[26] Dean M. Tullsen,et al. Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[27] Jonathan D Allen. Energy Efficient Adaptive Reed-Solomon Decoding System , 2008 .
[28] Jonathan Rose,et al. Application-specific customization of soft processor microarchitecture , 2006, FPGA '06.
[29] Dennis Goeckel,et al. A dynamically reconfigurable adaptive viterbi decoder , 2002, FPGA '02.
[30] Yiran Chen,et al. A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[31] Robert W. Jackson,et al. Interleaved Sparse Arrays for Polarization Control of Electronically Steered Phased Arrays for Meteorological Applications , 2012, IEEE Transactions on Geoscience and Remote Sensing.
[32] M. Hosomi,et al. A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[33] Scott A. Mahlke,et al. Efficient performance scaling of future CGRAs for mobile applications , 2012, 2012 International Conference on Field-Programmable Technology.
[34] Reiner W. Hartenstein,et al. Field-Programmable Logic Smart Applications, New Paradigms and Compilers , 1996, Lecture Notes in Computer Science.
[35] B. V. Essen,et al. Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency ∗ , 2007 .
[36] Carl Ebeling,et al. SPR: an architecture-adaptive CGRA mapping tool , 2009, FPGA '09.
[37] Cong Xu,et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[38] George Bourianoff,et al. Emerging Nanoscale Memory and Logic Devices: A Critical Assessment , 2008, Computer.
[39] Yiran Chen,et al. Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.
[40] Yunheung Paek,et al. Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.
[41] Irving S. Reed,et al. Reed-Solomon Codes , 1999 .
[42] Jason Cong,et al. FPGA Design Automation: A Survey , 2006, Found. Trends Electron. Des. Autom..
[43] Shoji Ikeda,et al. 2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[44] Ivan Saraiva Silva,et al. When reconfigurable architecture meets network-on-chip , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).
[45] C.H. Lam. The Quest for the Universal Semiconductor Memory , 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.
[46] Scott Hauck,et al. Reconfigurable computing: a survey of systems and software , 2002, CSUR.
[47] Fadi J. Kurdahi,et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.
[48] Iqbal Gondal,et al. Mobile Multimedia Communications: Concepts, Applications, and Challenges , 2007 .
[49] Russell Tessier,et al. c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Reconfigurable Computing for Digital Signal Processing: A Survey ∗ , 1999 .
[50] J. Otani,et al. A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme , 2006, 2006 IEEE Asian Solid-State Circuits Conference.
[51] Scott Hauck,et al. Issues and approaches to coarse-grain reconfigurable architecture development , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..
[52] D. Rouffet,et al. Convergence and Competition on the Way Towards 4G , 2007, 2007 IEEE Radio and Wireless Symposium.
[53] Shu Lin,et al. Error Control Coding , 2004 .